EP0466016A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Silicide/metal capacitor for polysilicon gate
Assignee: Texas Instruments Inc
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Filing: 1991-07-03
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Granted: —
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Expires: 2011-07-03
Abstract
Abstract The invention provides an integrated circuit capacitor 2 with a silicided 14 polysilicon electrode (which silicide has not been used as an etch stop) as a bottom plate and a metal layer 24/30 as a top plate. Subsequent to the formation of a patterned polysilicon layer, a multilevel dielectric 16 is formed, and a via is etched therethrough to a polysilicon capacitor bottom plate 10. Then the polysilicon bottom plate 10 is clad with a refractory metal silicide 14. The capacitor dielectric is then deposited, such a dielectric preferably consisting of an oxide/nitride 20/22 layered dielectric. Contacts are etched to diffusion and to polysilicon electrodes as desired, and metal is deposited and patterned to form the top electrode of the capacitor over the capacitor dielectric, and to make contact as desired to diffusion and to polysilicon.
Inventors
- 👤 James L. Paterson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 19:51
CPC Classifications
H; H10; H10D; H10D84/00; H10D1/00; H10D1/60; H10D1/68; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10B; H10B69/00
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
206 words
A floating-gate transistor formed at a surface of a semiconductor body, comprising: a field dielectric at said surface, to define a moat region not covered by said field dielectric; a source diffusion at a first portion of said moat region; a drain diffusion at a second portion of said moat region; a floating gate, comprising polycrystalline silicon, having a capacitor bottom plate section disposed over said field dielectric, and having a gate portion extending off of said field dielectric and disposed between said source and drain diffusions; a multilevel dielectric, disposed over said semiconductor body surface away from said capacitor bottom plate section; a silicide film, disposed on only a portion a top surface of said capacitor bottom plate section; a capacitor dielectric layer, disposed over and in contact with said silicide film at said capacitor bottom plate section, and disposed over said multilevel dielectric away from said capacitor bottom plate section; and a patterned conductor layer, comprising a metal layer, with a first portion, comprising a control gate, disposed over and in contact with said capacitor dielectric layer at said capacitor bottom plate section, and a second portion disposed over and in contact with at least one of said source diffusion and said drain diffusion.
Claim 2
Dependent Claim
37 words
The floating-gate transistor of Claim 1, wherein said control gate comprises: a first metal layer comprising titanium and tungsten in contact with said capacitor dielectric; and a second metal layer in contact with said first metal layer.
Claim 3
Dependent Claim
16 words
The floating-gate transistor of Claim 1, wherein said capacitor dielectric comprises silicon dioxide and silicon nitride.
Claim 4
Dependent Claim
23 words
The floating-gate transistor of Claim 1, wherein said silicide film, is also disposed on a portion, but not all of said moat region.
Claim 5
Dependent Claim
36 words
The floating gate transistor of claim 4, wherein said silicide film in said moat region is where said patterned conductor layer is in contact with at least one of said source diffusion and said drain diffusion.
Claim 6
Dependent Claim
18 words
The floating-gate transistor of Claim 3, wherein said layer of silicon nitride overlies said layer of silicon dioxide.
Claim 7
Independent Claim
215 words
A method for fabricating a floating-gate transistor at a surface of a semiconductor body, said method comprising the steps of: forming a field dielectric structure at said surface, to define a moat region not covered by said field dielectric structure; forming a source diffusion and a drain diffusion at said moat region; forming a floating gate, comprising polycrystalline silicon, said floating gate having a capacitor bottom plate section disposed over said field dielectric structure, and having a gate portion extending off of said field dielectric and disposed between said source and drain diffusions; forming a multilevel dielectric layer overall; removing a portion of said multilevel dielectric layer over said capacitor bottom plate section to expose a portion thereof; forming a silicide film, disposed on said exposed portion of said capacitor bottom plate section; forming a capacitor dielectric overall; removing a portion of said capacitor dielectric and said multilevel dielectric layer over said moat region to expose a portion thereof; and forming a patterned conductor layer, comprising a metal layer, with a first portion comprising a top plate disposed over and in contact with said capacitor dielectric layer at said capacitor bottom plate section, and a second portion disposed over and in direct contact with at least one of said source diffusion and said drain diffusion.
Claim 8
Dependent Claim
88 words
The method of Claim 7, wherein said step of forming said top plate comprises: forming a first metal layer in contact with said capacitor dielectric prior to the step of removing a portion of said multilevel dielectric layer over said moat region; and forming a second metal layer in contact with said first metal layer after said step of removing a portion of said multilevel dielectric layer over said moat region, wherein said second metal layer is in direct contact with said exposed portion of said moat region.
Claim 9
Dependent Claim
14 words
The method of Claim 8, wherein said first metal layer comprises titanium and tungsten.
Claim 10
Dependent Claim
34 words
The method of Claim 7, wherein said step of forming a capacitor dielectric comprises: forming a layer of silicon dioxide overall; and forming a layer of silicon nitride over said layer of silicon dioxide.
Claim 11
Dependent Claim
19 words
The method of Claim 7, wherein said depositing steps are performed by way of low pressure chemical vapor deposition.
Claim 12
Dependent Claim
75 words
The method of Claim 7, wherein said step of removing a portion of said multilevel dielectric layer over said capacitor bottom plate section to expose a portion thereof also exposes portions of said multilevel dielectric layer over said source or drain diffusions, and said step of forming a silicide film disposed on said exposed portion of said capacitor bottom plate section, also forms a silicide film on exposed portions of said source or drain diffusions.
Claim 13
Dependent Claim
119 words
A capacitor formed at a predetermined location at the surface of a semiconductor body, comprising: a field dielectric structure at said surface; a bottom plate, comprising polycrystalline silicon, disposed over said field dielectric structure; a multilevel dielectric, disposed over said surface away from the location of said capacitor; a silicide film, disposed at only a portion of a surface of said bottom plate; a capacitor dielectric layer, disposed over and in contact with said bottom plate at the location of said capacitor, and disposed over said multilevel dielectric away from the location of said capacitor; and a top plate, comprising a metal layer, disposed over and in contact with said capacitor dielectric layer at the location of said capacitor.
Claim 14
Independent Claim
111 words
A method for fabricating a capacitor at a surface of a semiconductor body, comprising the steps of: forming a field dielectric structure at said surface, to define a moat region not covered by said field dielectric structure; forming a bottom plate comprising polycrystalline silicon overlying said field dielectric structure; forming a multilevel dielectric layer overall; removing a portion of said multilevel dielectric layer over said bottom plate to expose a portion thereof; forming a silicide film at said exposed portion of said bottom plate; forming a capacitor dielectric over said silicide film; and forming a top plate comprising a metal layer in contact with said capacitor dielectric over said bottom plate.
Claim 15
Dependent Claim
75 words
The method of Claim 14, wherein said step of removing a portion of said multilevel dielectric layer over said capacitor bottom plate section to expose a portion thereof also exposes portions of said multilevel dielectric layer over said source or drain diffusions, and said step of forming a silicide film disposed on said exposed portion of said capacitor bottom plate section, also forms a silicide film on exposed portions of said source or drain diffusions.
References Cited (Backward Citations)
No citation records indexed.
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