EP0464667A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Power-on-clear signal generating circuit
Assignee: Toshiba Corp
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Filing: 1991-06-27
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Granted: —
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Expires: 2011-06-27
Abstract
Abstract The gate of an enhancement type N-channel MOS transistor (23) is connected to the drain of a P-channel MOS transistor (22), which serves as a load element. The source and drain of the N-channel MOS transistor (23) is connected to the ground voltage GND. The input terminal of a Schmitt trigger circuit (25) is the connection node which connects the drain of the P-channel MOS transistor (22) and the gate of the N-channel MOS transistor (23) to each other. The output terminal (26) from which a power-on-clear signal (POC) is output is connected to the output terminal of the Schmitt trigger circuit (25).
Inventors
- 👤 Hisashi c/o Intellectual Hashimoto
- 👤 Toshiya Kato
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 22:08
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H03K17/223
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
92 words
A power-on-clear signal generating circuit comprising: a first power source node (21) to which a first power source voltage (VDD) is applied; a second power source node (24) to which a second power source voltage is applied; a load element (22), an end of which is connected to said first power source node; and a first MOS transistor (23) of an enhancement type, a gate of which is connected to an other end of said load element, and a source and drain of which are connected to said second power source node.
Claim 2
Dependent Claim
55 words
A power-on-clear signal generating circuit according to claim 1, characterized in that said load element is composed of a second MOS transistor (22) of an enhancement type, and includes a gate, source, and drain connected to the second power source node, the first power source node, and the gate of said first MOS transistor, respectively.
Claim 3
Dependent Claim
22 words
A power-on-clear signal generating circuit according to claim 1, characterized in that said first MOS transistor is of an N channel type.
Claim 4
Dependent Claim
22 words
A power-on-clear signal generating circuit according to claim 2, characterized in that said second MOS transistor is of a P channel type.
Claim 5
Dependent Claim
141 words
A power-on-clear signal generating circuit comprising: a first power source node (21) to which a first power source voltage (VDD) is applied; a second power source node (24) to which a second power source voltage is applied; a load element (22), an end of which is connected to said first power source node; a first MOS transistor (23) of an enhancement type, a gate of which is connected to an other end of said load element, and a source and drain of which are connected to said second power source node; and a signal generating circuit (25,27) for outputting a power-on-clear signal, an input terminal of which is connected to a connection node between said load element and the gate of said first MOS transistor so as to receive a signal from the connection node at a predetermined circuit threshold voltage.
Claim 6
Dependent Claim
55 words
A power-on-clear signal generating circuit according to claim 5, characterized in that said load element is composed of a second MOS transistor (22) of an enhancement type, and includes a gate, source, and drain connected to the second power source node, the first power source node, and the gate of said first MOS transistor, respectively.
Claim 7
Dependent Claim
22 words
A power-on-clear signal generating circuit according to claim 5, characterized in that said first MOS transistor is of an N channel type.
Claim 8
Dependent Claim
22 words
A power-on-clear signal generating circuit according to claim 6, characterized in that said second MOS transistor is of a P channel type.
Claim 9
Dependent Claim
21 words
A power-on-clear signal generating circuit according to claim 5, characterized in that said signal generating circuit is a Schmitt trigger circuit.
Claim 10
Dependent Claim
20 words
A power-on-clear signal generating circuit according to claim 5, characterized in that said signal generating circuit is an inverter (27).
Claim 11
Dependent Claim
21 words
A power-on-clear signal generating circuit according to claim 5, characterized in that said signal generating circuit is a buffer circuit (28).
References Cited (Backward Citations)
No citation records indexed.
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