EP0464620A2
Expired / Lapsed
EP
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Image information control apparatus and display system
Assignee: Canon Inc
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Filing: 1991-06-26
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Granted: —
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Expires: 2011-06-26
Abstract
Abstract An image information control apparatus includes a partial write detector having at least two types of memory units for detecting and storing addresses accessed to a VRAM in units of lines in a scanning direction, thereby repeating the detection and the storage at different cycles, a circuit for performing calculations to recognize partial write information from contents of each of the memory units, memory units for storing the respective calculation results, a circuit for comparing the memory contents to determine a size relationship between partial write areas, a partial write ID signal controller for controlling a partial write ID signal on the basis of the size relationship between partial write areas and externally outputting the signal, and a circuit for, even when partial writing is being executed, forcibly interrupting the partial writing in accordance with a state of an external refresh control signal, starting refresh, and restarting the partial writing in accordance with a partial write state and a change in state of the refresh control signal.
Inventors
- 👤 Hiroshi C/O Canon Kabushiki Kaisha Inoue
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 15:41
CPC Classifications
G; G09; G09G; G09G3/00; G09G3/20; G09G3/34; G09G3/36; G09G3/3611; G09G3/3648; G09G3/3651; G09G3/3622; G09G3/3629; G09G2310/00; G09G2310/04
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
167 words
An image information control apparatus comprising: a partial write detector having at least two types of memory units for detecting and storing addresses accessed to a VRAM in units of lines in a scanning direction, thereby repeating the detection and the storage at different cycles; a circuit for performing calculations to recognize partial write information from contents of each of said memory units; memory units for storing the respective calculation results; a circuit for comparing the memory contents to determine a size relationship between partial write areas; a partial write ID signal controller for controlling a partial write ID signal on the basis of the size relationship between partial write areas and externally outputting the signal; and a circuit for, even when partial writing is being executed, forcibly interrupting the partial writing in accordance with a state of an external refresh control signal, starting refresh, and restarting the partial writing in accordance with a partial write state and a change in state of the refresh control signal.
Claim 2
Dependent Claim
69 words
An apparatus according to claim 1, wherein the partial write information detected in units of lines by said memory units are identified as continuous line address groups in the scan line direction from the accessed address data, the number of addresses, a start line address or an end line address, or the number of lines is calculated for each group, and a total number of accessed lines is calculated.
Claim 3
Dependent Claim
18 words
An apparatus according to claim 1, wherein only access to said VRAM performed during writing is rendered valid.
Claim 4
Dependent Claim
36 words
An apparatus according to claim 1, wherein a detection period (sampling period) of said memory units for executing detection and storage in units of lines in the scan direction is shorter than a storage period thereof.
Claim 5
Dependent Claim
50 words
An apparatus according to claim 1, wherein when the size relationship between the partial write areas obtained from the partial write information is to be determined, a detection period (sampling period) of a memory unit having partial write information of a larger area is shorter than a storage period thereof.
Claim 6
Dependent Claim
55 words
An apparatus according to claim 1, wherein a cycle of determining the size relationship between the partial write areas obtained from the partial write information is synchronized with a cycle of said partial write detector for repeating detection and storage such that the cycles are integer multiples with respect to said different memory units, respectively.
Claim 7
Dependent Claim
175 words
A display system comprising: an image information control apparatus having a partial write detector having at least two types of memory units for detecting and storing addresses accessed to a VRAM in units of lines in a scanning direction, thereby repeating the detection and the storage at different cycles, a circuit for performing calculations to recognize partial write information from contents of each of said memory units, memory units for storing the respective calculation results, a circuit for comparing the memory contents to determine a size relationship between partial write areas, a partial write ID signal controller for controlling a partial write ID signal on the basis of the size relationship between partial write areas and externally outputting the signal, and a circuit for, even when partial writing is being executed, forcibly interrupting the partial writing in accordance with a state of an external refresh control signal, starting refresh, and restarting the partial writing in accordance with a partial write state and a change in state of the refresh control signal; and a display panel.
Claim 8
Dependent Claim
69 words
A system according to claim 7, wherein the partial write information detected in units of lines by said memory units are identified as continuous line address groups in the scan line direction from the accessed address data, the number of addresses, a start line address or an end line address, or the number of lines is calculated for each group, and a total number of accessed lines is calculated.
Claim 9
Dependent Claim
18 words
A system according to claim 7, wherein only access to said VRAM performed during writing is rendered valid.
Claim 10
Dependent Claim
36 words
A system according to claim 7, wherein a detection period (sampling period) of said memory units for executing detection and storage in units of lines in the scan direction is shorter than a storage period thereof.
Claim 11
Dependent Claim
50 words
A system according to claim 7, wherein when the size relationship between the partial write areas obtained from the partial write information is to be determined, a detection period (sampling period) of a memory unit having partial write information of a larger area is shorter than a storage period thereof.
Claim 12
Dependent Claim
55 words
A system according to claim 7, wherein a cycle of determining the size relationship between the partial write areas obtained from the partial write information is synchronized with a cycle of said partial write detector for repeating detection and storage such that the cycles are integer multiples with respect to said different memory units, respectively.
References Cited (Backward Citations)
No citation records indexed.
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