EP0464601A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Arithmetic operation system

Assignee: NEC Corp

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Filing: 1991-06-25

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Granted: —

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Expires: 2011-06-25

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Abstract

Abstract An arithmetic operation system includes a plurality of cascaded arithmetic units each receiving operation data and an input carry and outputting an operation result data and an output carry. A carry control indication register is provided for storing carry control information for each of the plurality of cascaded arithmetic units. A carry controller is provided for each of the cascaded arithmetic units so as to receive a corresponding carry control bit from the carry control indication register. The carry controller operates to modify an output carry outputted from the corresponding arithmetic unit on the basis of the received catty control bit, so as to supply the modified carry to an adjacent more significant bit arithmetic unit.

Inventors

👤 Nobuko c/o NEC Corporation Matsuda

Bibliographic Details

Application Number —

Jurisdiction EP

Data Source google_patents

Last Synchronized 2026-11-09 09:30

CPC Classifications

G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/57; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3828

Claims Analysis

Total Claims: 2

Claim 1

Independent Claim 111 words

An arithmetic operation system which includes a plurality of cascaded arithmetic units each receiving operation data and an input carry and outputting an operation result data and an output carry, comprising a carry control indication register for storing carry control information for each of said plurality of cascaded arithmetic units, and a plurality of carry controllers each provided for a corresponding one of said plurality of cascaded arithmetic units, said carry controller receiving corresponding carry control information from said carry control indication register and operating to modify an output carry outputted from the corresponding arithmetic unit so as to supply the modified carry to an adjacent more significant bit arithmetic unit.

Claim 2

Dependent Claim 154 words

An arithmetic operation system claimed in Claim 1 wherein each of said arithmetic units has its carry output connected to the carry input of an adjacent more significant bit arithmetic unit through a first transfer gate which is controlled by a corresponding bit of said carry control information stored in said carry control indication register, said carry input of an adjacent more significant bit arithmetic unit being also connected to receive a fixed level through a second transfer gate which is also controlled by said corresponding bit of said carry control information in such a manner that when said corresponding bit of said carry control information indicates allowance of a carry propagation, said first transfer gate is opened and said second transfer gate is closed, and when said corresponding bit of said carry control information indicates inhibit of a carry propagation, said first transfer gate is closed and said second transfer gate is opened.

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