EP0464494A2
Expired / Lapsed
EP
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A high performance pipelined emulator
Assignee: Bull HN Information Systems Inc
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Filing: 1991-06-20
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Granted: —
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Expires: 2011-06-20
Abstract
Abstract The emulator includes first and second pipelined stages connected through a bidirectional bus for executing source instructions normally executed by a different/source computer in a highly overlapped manner. The first stage includes an emulator chip which performs the function of fetching and decoding each source instruction stored in cache memory resulting in the generation of a number of vector addresses required for executing the instruction by the second stage. The second stage includes a high performance microprocessor chip having on-chip instruction and data caches for storing a plurality of emulation subroutines and data fetched during subroutine execution. In pipelined fashion, the emulator chip fetches and decodes each source instruction which generates a vector branch address which is loaded into the branch vector register while the microprocessor chip fetches and executes emulation subroutines specified by the vector address transferred via the bus for each previously decoded source instruction.
Inventors
- 👤 Steven S. Smith
- 👤 Arnold J. Smith
- 👤 Amy E. Gilfeather
- 👤 Richard P. Brown
- 👤 Thomas F. Joyce
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 10:18
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3804; G06F9/3017; G06F9/30174; G06F9/3877; G06F9/3879
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
206 words
A pipelined emulator for executing a set of source instructions executable by a general purpose computer having a specific architecture, said emulator comprising: a first pipelined stage coupled to an instruction cache, said first pipelined stage including an emulation chip for fetching, decoding each source instruction stored in said instruction cache and for generating a number of vector addresses for identifying a corresponding number of emulation subroutines required for executing said each source instruction; a second pipelined stage, said second stage including a high performance microprocessor chip and instruction and data caches tightly coupled to said microprocessor chip, said instruction cache storing a plurality of emulation subroutines for executing said set of source instructions and said data cache for storing data fetched during execution of said emulation subroutines; and, a bidirectional bus interconnecting said first and second pipeline stages for transfer of said number of vector addresses between said first and second pipelined stages, said emulation chip decoding and generating vector addresses for each source instruction in parallel with said microprocessor chip fetching and executing those emulator subroutines stored in said instruction cache associated therewith specified by the vector addresses transferred by said bidirectional bus for emulating said general purpose computer in executing said source instruction.
Claim 2
Dependent Claim
98 words
The emulator of claim 1 wherein said microprocessor chip includes branch vector apparatus, said apparatus being connected to said bidirectional bus for receiving and storing each vector address generated and transferred by said emulation chip and said apparatus including output means for generating an external signal on said bus signaling each time said microprocessor chip accesses said each vector address to fetch one of said emulation subroutines from said instruction cache, enabling said emulation chip to transfer a next vector address to said branch vector apparatus thereby eliminating said second pipeline stage having to make off chip accesses.
Claim 3
Dependent Claim
92 words
The emulator of claim 2 wherein said branch vector apparatus further includes a branch vector register connected to said bus for receiving and storing said each vector address, read and write indicator means for storing signals received from said microprocessor and emulation chips indicating when said branch vector register has been accessed and updated respectively; and means for connecting said read indicator means to said output means for causing said output means to generate said external signal on said bus each time said read indicator means is set to an active state.
Claim 4
Dependent Claim
53 words
The emulator of claim 3 wherein said microprocessor chip includes a branch vector instruction facility for testing said write indicator means for determining when said write indicator means is set to an active state enabling said microprocessor chip to branch to one of said plurality of emulator subroutines stored in said instruction cache.
Claim 5
Dependent Claim
48 words
The emulator of claim 4 wherein each of said plurality of emulation subroutines includes a plurality of reduced instruction set (RISC) type of instructions and a branch vector instruction as a last one of said plurality of RISC type of instructions coded for fetching a next emulation subroutine.
Claim 6
Dependent Claim
30 words
The emulator of claim 1 wherein said instruction and data caches are located on said microprocessor chip and said microprocessor chip is a standard reduced instruction set (RISC) type chip.
Claim 7
Dependent Claim
151 words
The emulator of claim 3 wherein said emulation chip includes a subroutine and control store sequencer coupled to a subroutine address control store and an instruction decode unit, said instruction decode unit being coupled to said instruction cache and in response to fetching and decoding said each source instruction, said unit generating a starting address for accessing said subroutine address control store, said subroutine control store having a plurality of addressable storage locations for storing microinstructions for controlling emulation chip operations, each of a number of said microinstructions containing a vector address for specifying a starting address of a different one of said plurality of emulation subroutines and said control store being connected to said bus, said control store in response to said starting address reading out a specified one of said number of said microinstructions for generating one of said number of vector addresses for transfer to said microprocessor chip.
Claim 8
Dependent Claim
69 words
The emulator of claim 7 wherein said subroutine and control store sequencer is connected to said output means of said microprocessor chip, said sequencer in response to each said external signal advancing said subroutine address control store to access a microinstruction for reading out another one of said number of said microinstructions for generating a next one of said number of vector addresses for transfer to said microprocessor chip.
Claim 9
Dependent Claim
38 words
The emulator of claim 8 wherein said number of said microinstructions include vector addresses for specifying emulation subroutines for performing address development and execution operation phases required for emulating execution of source instructions by said general purpose computer.
Claim 10
Dependent Claim
221 words
A pipelined emulator for executing source instructions executable by a general purpose computer, said emulator comprising: a microprocessor chip including on-chip instruction and data caches, said instruction cache storing a plurality of emulation subroutines for said source instructions; an emulation chip coupled to an instruction cache for storing a plurality of source instructions of a program to be emulated by said emulator, said emulation chip including: an instruction unit coupled to said instruction cache for fetching and decoding each source instruction and subroutine address control store coupled to said instruction unit, said store including a plurality of locations, each for storing a vector address identifying a different one of said plurality of emulation subroutines; and, a bidirectional bus interconnecting said microprocessor and emulation chips for transferring information according to a standard protocol, said emulation instruction unit during a first phase of operation decoding each source instruction fetched from said instruction cache and causing said control store to read out said vector address for transfer to said microprocessor chip using said standard protocol and during a second phase of operation, said microprocessor chip fetching said vector address previously transferred to said microprocessor chip during said first phase and executing instructions of a specified one of said emulation subroutines thereby enabling the execution of source instructions in a two-stage pipelined mode of operation.
Claim 11
Dependent Claim
97 words
The emulator of claim 10 wherein said microprocessor chip includes branch vector apparatus, said apparatus being connected to said bidirectional bus for receiving and storing each vector address generated and transferred by said emulation chip and said apparatus including output means for generating an external signal on said bus signaling each time said microprocessor chip accesses said each vector address to fetch one of said emulation subroutines from said instruction cache, enabling said emulation chip to transfer a next vector address to said branch vector apparatus thereby eliminating said microprocessor chip having to make off chip accesses.
Claim 12
Dependent Claim
89 words
The emulator of claim 1 wherein said branch vector apparatus further includes a branch vector register connected to said bus for receiving and storing said each vector address, read and write indicator means for storing signals received from said microprocessor and emulation chips indicating when said branch vector register has been accessed and updated respectively; and means for connecting said read indicator means to said output means for causing said output means to generate said external signal each time said read indicator means is set to an active state.
Claim 13
Dependent Claim
53 words
The emulator of claim 12 wherein said microprocessor chip includes a branch vector instruction facility for testing said write indicator means for determining when said write indicator means is set to an active state enabling said microprocessor chip to branch to one of said plurality of emulator subroutines stored in said instruction cache.
Claim 14
Dependent Claim
48 words
The emulator of claim 13 wherein each of said plurality of emulation subroutines includes a plurality of reduced instruction set (RISC) type of instructions and a branch vector instruction as a last one of said plurality of RISC type of instructions coded for fetching a next emulation subroutine.
Claim 15
Dependent Claim
149 words
The emulator of claim 3 wherein said emulation chip further includes a subroutine and control store sequencer coupled to said subroutine address control store and instruction decode unit, said instruction decode unit in response to fetching and decoding said each source instruction, generating a starting address for accessing said subroutine address control store, said subroutine control store having a plurality of addressable storage locations for storing microinstructions for controlling emulation chip operations, each of a number of said microinstructions containing said vector address for specifying a starting address of said different one of said plurality of emulation subroutines and said control store being connected to said bus, said control store in response to said starting address reading out a specified one of said number of said microinstructions for applying one of said number of vector addresses to said bus for transfer to said microprocessor chip using said standard protocol.
Claim 16
Dependent Claim
80 words
The emulator of claim 15 wherein said subroutine and control store sequencer is connected to receive said external signal from said output means of said microprocessor chip, said sequencer in response to each said external signal advancing said subroutine address control store to access a microinstruction for reading out another one of said number of said microinstructions for generating a next one of said number of vector addresses for transfer to said microprocessor chip during said first phase of operation.
Claim 17
Dependent Claim
38 words
The emulator of claim 16 wherein said number of said microinstructions include vector addresses for specifying emulation subroutines for performing address development and execution operation phases required for emulating execution of source instructions by said general purpose computer.
Claim 18
Independent Claim
140 words
A method of operating an emulator for executing source instructions executable by a general purpose computer in a highly efficient manner, said method comprising the steps of: (a) fetching, decoding and generating a branch vector address by an emulator chip of a pipeline stage for each source instruction during a first phase of operation; (b) transferring the branch vector address to a microprocessor chip of a second pipeline stage through a bidirectional bus used to interconnect said chips; and, (c) fetching and executing instructions of one of a plurality of emulation subroutines stored in an on-chip instruction cache of said microprocessor chip specified by the branch vector address transferred during step b during a second phase of operation thereby enabling said first and second stages of said emulator to execute each said source instruction in a highly overlapped pipelined fashion.
Claim 19
Dependent Claim
43 words
The method of claim 18 wherein step c further includes the step of executing a plurality of reduced instruction set (RISC) instructions of said one of said plurality of emulation subroutines for emulating said general purpose computer in executing said each source instruction.
References Cited (Backward Citations)
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