EP0463752A2
Expired / Lapsed
EP
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Pattern matching circuit
Assignee: Digital Equipment Corp
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Filing: 1991-06-05
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Granted: —
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Expires: 2011-06-05
Abstract
Abstract The invention is a pattern matcher which (i) compares two or more multi-symbol data patterns, symbol-by-symbol, and detects any mis-matches, or errors, (ii) combines into a relatively small number of encoded bits information relating to the number of errors, and (iii) examines a single encoded bit to determine if the two patterns "match", i.e., if they differ by less than a predetermined number of symbols, or error threshold. The invention further includes a multi-bit output signal which may be used to determine, for patterns which match, the actual number of errors.
Inventors
- 👤 John E. Deroo
- 👤 Robert C. Frame
- 👤 Bernardo Rub
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 08:41
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/04; H04L7/041; H04L7/042; G; G06; G06F; G06F7/00; G06F7/02; G06F7/60; G06F7/607; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1816; G06F2207/00; G06F2207/02; G06F2207/025
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
203 words
A pattern matcher comprising: A. comparison means for comparing symbol-by-symbol two or more data patterns and producing a multibit error pattern that indicates which particular symbols do not match; B. an encoder for -- i. separating said error pattern into m segments, and ii. encoding each of said segments to produce m corresponding multi-bit code words, with each bit location of each of said code words being associated with a particular number of errors in the corresponding segment, said encoder setting the bits of said code words such that the position of the highest order set bit in a code word indicates the number of errors in the associated segment; C. combining means for combining said code words to form a multi-bit sum total, with each bit location of said sum total being associated with a range of numbers of errors, said combining means setting the bit corresponding to the range encompassing the number of errors in the associated segments; and D. a detector for indicating that the patterns match by determining that the sum total bit corresponding to a predetermined minimum pattern-matching error threshold is not set, said detector means detecting that the patterns do not match when said bit is set.
Claim 2
Dependent Claim
74 words
The pattern matcher of claim 1, wherein said pattern matcher further includes a second detector means for detecting deterioration of a storage medium on which a predetermined pattern is stored, said second detector examining the state of the bits which are above a predetermined threshold in a number of sum totals and indicating deterioration of the storage medium if the number of said sum totals with such bits set is above a predetermined number.
Claim 3
Dependent Claim
30 words
The pattern matcher of claim 1, wherein said combining means sets a single bit in said code word sum for all numbers of errors above a predetermined maximum pattern-matching threshold.
Claim 4
Dependent Claim
57 words
The pattern matcher of claim 1, wherein said detector indicates a match if a bit of said sum total which corresponds to an error threshold above said predetermined minimum pattern matching threshold is not set when the bit corresponding to said predetermined minimum pattern matching threshold is set in a predetermined number of previously generated sum totals.
References Cited (Backward Citations)
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