EP0463331A2
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EP
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An improved method for programming a non-volatile memory
Assignee: Texas Instruments Inc
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Filing: 1991-05-07
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Granted: —
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Expires: 2011-05-07
Abstract
Abstract An improved method is provided for programming a non-volatile memory cell formed at a face of a layer of semiconductor 12 of a first conductivity type and having a source region 14 in a drain 16 of a second conductivity type spaced by a channel 18. A floating gate 22 is disposed insulatively adjacent channel 18 and a control gate 24 is disposed insulatively adjacent floating gate 22. The source region 14 is grounded while a first voltage is applied to the drain region 16. A time varying voltage pulse is applied to the control gate such that the potential of floating gate 22 remains substantially constant as electrons are accumulated on floating gate 22.
Inventors
- 👤 Cetin Kaya
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 20:58
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/32
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
107 words
A method for programming a non-volatile memory cell formed at a face of a layer of semiconductor of a first conductivity type, and including first and second diffused regions of a second conductivity type spaced by a channel, a floating gate insulatively adjacent the channel, and a control gate insulatively adjacent the floating gate, comprising the steps of: applying a first voltage to the first diffusion region; applying a second voltage to the second diffused region; and applying a time varying voltage pulse to the control gate such that the potential of the floating gate remains substantially constant as electrons are injected on to the floating gate.
Claim 2
Dependent Claim
34 words
The method of Claim 1, wherein the time varying voltage pulse is shaped to maintain the potential of the floating gate at a level approximating the voltage being applied to the second diffused region.
Claim 3
Dependent Claim
24 words
The method of Claim 1, wherein the time varying voltage pulse is substantially a ramp function from a third voltage to a fourth voltage.
Claim 4
Dependent Claim
15 words
The method of Claim 3, wherein said third voltage is less than said fourth voltage.
Claim 5
Dependent Claim
23 words
The method of Claim 1, wherein the time varying voltage pulse includes a step function from a third voltage to a fourth voltage.
Claim 6
Dependent Claim
15 words
The method of Claim 5, wherein said third voltage is less than said fourth voltage.
Claim 7
Independent Claim
107 words
A method for programming a floating gate avalanche injection metal oxide semiconductor non-volatile memory cell, including a source and a drain region spaced by a channel, a floating gate insulatively overlying the channel, and a control gate insulatively overlying the floating gate, comprising the steps of: applying a first voltage to the drain region; applying a second voltage to the source region to create a current between the source and the drain; and applying a time varying voltage pulse to the control gate to induce a voltage on the floating gate such that a substantially constant gate current is generated between the channel and the floating gate.
Claim 8
Dependent Claim
23 words
The method of Claim 7, wherein the voltage pulse increases in a substantially linear manner from a third voltage to a fourth voltage.
Claim 9
Dependent Claim
21 words
The method of Claim 8, wherein the first voltage is approximately 8 volts and the second voltage is approximately 12 volts.
Claim 10
Dependent Claim
21 words
The method of Claim 9, wherein the voltage pulse has a time duration in the range of 10 to 100 microseconds.
Claim 11
Dependent Claim
22 words
The method of Claim 7, wherein the voltage pulse amplitude steps up from a first lower voltage to a second higher voltage.
Claim 12
Independent Claim
49 words
A method of programming a non-volatile memory by hot electron injection into a floating gate, comprising the steps of: generating a voltage differential between source and drain regions; and controlling the voltage of the floating gate to counter deviations in the floating gate voltage away from an optimum voltage.
Claim 13
Dependent Claim
29 words
The method of Claim 12, wherein said controlling step comprises the step of applying a voltage signal to a control gate which is electrically coupled to the floating gate.
Claim 14
Dependent Claim
28 words
The method of Claim 13, wherein said applying step comprises the step of applying a voltage signal to the control gate which varies as a function of time.
Claim 15
Dependent Claim
32 words
The method of Claim 14, wherein said step of applying a variable voltage signal comprises the step of applying a voltage signal to the control gate which varies substantially linearly with time.
Claim 16
Dependent Claim
23 words
The method of Claim 14, wherein said step of applying a variable voltage signal comprises the step of applying a step voltage signal.
Claim 17
Dependent Claim
19 words
The method of Claim 12, wherein the optimum voltage equals the voltage at which the gate current is maximized.
Claim 18
Dependent Claim
21 words
The method of Claim 12, wherein the optimum floating gate voltage is approximately equal to the voltage applied to the drain.
Claim 19
Dependent Claim
62 words
A memory cell array comprising: a plurality of non-volatile memory cells each having a control gate, a floating gate, a source and a drain; and control circuitry coupled to said cells operable to apply a time-varying voltage pulse to selected said control gates such that respective floating gates associated with said selected control gates are charged with a substantially constant gate current.
Claim 20
Dependent Claim
34 words
The memory cell array of Claim 19, wherein said control circuitry is operable to apply a time-varying voltage pulse which ramps in a substantially linear fashion from a first voltage to a second voltage.
Claim 21
Dependent Claim
29 words
The memory cell array of Claim 20, wherein said control circuitry is operable to apply a time-varying voltage pulse which steps from a first voltage to a second voltage.
Claim 22
Dependent Claim
142 words
An array of non-volatile memory cells formed in columns and in rows at an angle to the columns, at the face of a layer of semiconductor of a first conductivity type, comprising: for each column, an elongated drain region of a second conductivity type opposite said first conductivity type, forming a first bit line; for each column, an elongated source region of said second conductivity type forming a second bit line substantially and parallel to said first bit line and spaced therefrom by a channel; for each cell, a floating gate insulatively adjacent a portion of a respective channel; for each row, an elongate control gate insulatively adjacent said floating gates in said row, forming a wordline; and a row decoder coupled to said wordlines in said array, said row decoder operable to apply a time varying voltage pulse to said wordlines.
Claim 23
Dependent Claim
33 words
The array of Claim 12, wherein said row decoder is operable to apply a time varying voltage pulse which ramps in a substantially linear fashion from a first voltage to a second voltage.
Claim 24
Dependent Claim
31 words
The array of Claim 12, wherein said row decoder is operable to apply a time varying voltage pulse which includes a voltage step from a first voltage to a second voltage.
References Cited (Backward Citations)
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