Multiwindow display control method and apparatus

Claim 2

A multiwindow display control method as claimed in claim 1, wherein said steps of generating a second group number, of determining a group of windows, of determining a window and of displaying the pixel data, are carried out pixel by pixel.

Claim 3

A multiwindow display control method as claimed in claim 1 or 2, further comprising, before the step of determining a group of windows, a step of storing a display enable region signal (DE n ) in said frame memory control means, said display enable region signal indicating whether or not the display of pixels includes each pixel in each of said windows, said step of determining a window including a step of determining the window to be displayed when said display enable region signal indicates that the display of the pixel data can be made.

Claim 4

A multiwindow display control method as claimed in any of claims 1 to 3, wherein said step of displaying pixels is carried out by absolute coordinates on a display screen.

Claim 5

A multiwindow display control method as claimed in any of claims 1 to 4, wherein said step of generating a second group number is carried out group window by group window.

Claim 6

A multiwindow display control method as claimed in any of claims 1 to 5, further comprising, after said step of storing a priority number, a step of generating a group window region signal (GW) representing the region of each group window when displayed on a display screen, said step of displaying a window is carried out by relative coordinates with respect to said group window region.

Claim 7

A multiwindow display control method for controlling a display of multiwindows consisting of a plurality of group of windows each including a plurality of windows, characterized in that: as parameters for controlling a display of said windows, each of said windows is provided with; a group number (GN) for identifying a group of windows to which the window belongs; and a priority number (PN) for indicating a priority of a display in said group of windows; the display control among said windows being carried out by combining one of said group numbers and one of said priority numbers assigned to each of said windows.

Claim 8

A multiwindow display control method as claimed in claim 7, characterized in that: a region of each of said group of windows on a display screen is individually determined, and the display position of each window in each of said group of windows is controlled by relative coordinates with respect to said determined region.

Claim 9

A multiwindow display control apparatus for controlling a display of multiwindows consisting of a plurality of groups of windows each including a plurality of windows, comprising: plurality of frame memory control means (12-i) each for storing pixel data to be displayed on one of said windows, a first group number of a group of windows to which the window belongs, and a priority number for identifying a display priority in the windows included in the same group of windows; outline generating means (10) for generating a second group number each identifying one of said group of windows; pixel data arbitration means (14), operatively connected to said frame memory control means (12-i) and to said outline generating means (10) for determining a group of windows having said first group number (GN) which coincides with said second group number, and for determining a window to be displayed having a priority number of the highest priority in the determined group of windows; and display means (16), operatively connected to said pixel data arbitration means (14), for displaying pixel data of the determined window.

Claim 10

A multiwindow display control apparatus as claimed in claim 9, wherein said outline generating means (10) comprises a group number storing frame memory (11), said group number being read from said group number storing memory pixel by pixel, and said pixel data arbitration means (14) determines the window to be displayed pixel by pixel.

Claim 11

A multiwindow display control apparatus as claimed in claim 9 or 10, wherein said pixel data arbitration means (14) comprises a plurality of pixel data arbitration circuits (15-i) respectively connected to said frame memory control means (12-i), said pixel data arbitration circuits (15-i) being connected to each other by a daisy chain structure.

Claim 12

A multiwindow display control apparatus as claimed in claim 11, wherein each of said pixel data arbitration circuits (15-i) comprises: first comparing means (151) for detecting a coincidence between said group number (GN n-1 ) generated from said outline generating means (10) and a group number (GN n ) stored in the corresponding frame memory control means (12-n); second comparing means (152) for detecting whether a priority number (PN n ) stored in the corresponding frame memory control means (12-n) is larger than a priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit (15-(n-1)); and selecting means (154) for outputting, when said first comparing means detects the coincidence and said second comparing means detects that the priority number (PN n ) stored in the corresponding frame memory control means (12-n) is larger than the priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit, the priority number (PN n ) and the pixel data (PD n ) stored in the corresponding frame memory control means (12-n), and for outputting, when said first comparing means does not detect the coincidence or when said second comparing means detects that the priority number (PN n ) stored in the corresponding frame memory control means (12-n) is smaller than the priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit, the priority number (PN n-1 ) and the pixel data (PD n-1 ) sent from the previous stage pixel data arbitration circuit, said group number (GN n-1 ) generated from said outline generating means (10) being passed to the next stage pixel data arbitration circuit (15-(n+1)).

Claim 13

A multiwindow display control apparatus as claimed in claim 12, wherein each of said frame memory control means (15-n) stores a display enable signal (DE n ) indicating whether or not each pixel is allowed to be displayed, and said selecting means (154) selects said priority number (PN n ) and the pixel data (PD n ) stored in the corresponding frame memory control means (12-n) to be output to the next stage pixel data arbitration circuit (15-(n+1)) when said display enable signal (DE n ) indicates that the pixel is allowed to be displayed.

Claim 14

A multiwindow display control apparatus as claimed in claim 11, 12 or 13 wherein each of said pixel data arbitration circuits (15-i) comprises: first comparing means (171) for detecting a coincidence between said group number (GN n-1 ) generated from said outline generating means (10) and a group number (GN n ) stored in the corresponding frame memory control means (12-n); second comparing means (172) for detecting whether a priority number (PN n ) stored in the corresponding frame memory control means (12-n) is larger than a priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit (15-(n-1)); selecting means (176) for outputting, when said first comparing means detects a coincidence and said second comparing means detects that the priority number (PN n ) stored in the corresponding frame memory control means (12-n) is larger than the priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit, the priority number (PN n ) in the corresponding frame memory control means (12-n), and for outputting, when said first comparing means does not detect a coincidence or when said second comparing means detects that the priority number (PN n ) stored in the corresponding frame memory control means (12-n) is smaller than the priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit, the priority number (PN n-1 ) sent from the previous stage pixel data arbitration circuit; third comparing means (173) for detecting a coincidence between the priority number (PN n-1 ) sent from the previous stage pixel data arbitration circuit (15-(n-1)) and the priority number (PN n ) stored in the corresponding frame memory control means (12-n); and pixel data calculating means (177) for outputting, when said first comparing means detects a coincidence and said second comparing means detects that the priority number (PN n ) stored in the corresponding frame memory control means (12-n) is larger than the priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit, the pixel data (PD n ) in the corresponding frame memory control means (12-n); for outputting, when said first comparing means does not detect a coincidence or when said second comparing means detects that the priority number (PN n ) stored in the corresponding frame memory control means (12-n) is smaller than the priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit, the pixel data (PD n-1 ) sent from the previous stage pixel data arbitration circuit; and for performing, when said first comparing means and said third comparing means respectively detect the coincidences, a predetermined calculation between said pixel data (PD n-1 ) sent from the previous stage pixel data arbitration circuit (15-(n-1)) and said pixel data (PD n ) in the corresponding frame memory control means (12-n), and for outputting the calculated result; said group number (GN n-1 ) generated from said outline generating means (10) being passed to the next stage pixel data arbitration circuit (15-(n+1)).

Claim 15

A multiwindow display control apparatus as claimed in claim 13 or 14, wherein each of said frame memory control means (15-n) stores a display enable signal (DE n ) indicating whether or not each pixel is allowed to be displayed; said selecting means (176) selecting said priority number (PN n ) stored in the corresponding frame memory control means (12-n) to be output to the next stage pixel data arbitration circuit (15-(n+1)) when said display enable signal (DE n ) indicates that the pixel is allowed to be displayed; and said pixel data calculating means (177) outputting said pixel data (PD n ) stored in the corresponding frame memory control means (15-n) or performing said predetermined calculation when said display enable signal (DE n ) indicates that the pixel is allowed to be displayed.

Claim 16

A multiwindow display control apparatus as claimed in any of claims 9 to 15, characterized in that: each of said pixel data arbitration circuits comprises means (186) for forcibly changing the group numbers, the priority numbers, and the pixel data signals; and each of said frame memory control units comprises forcible change instructing means (CG n ) for instructing the corresponding each pixel data arbitration circuit to forcibly change the signals, when the forcibly change instructing means outputs an enable signal for a forcible change, all of the group number, the priority number, and the pixel data output from the previous stage pixel data arbitration circuit are forcibly replaced by the group number, the priority number, and the pixel data of the present stage frame memory control unit, and are output to the next stage pixel data arbitration circuit.

Claim 17

A multiwindow display control apparatus as claimed in any of claims 9 to 16, wherein: each of said frame memory control means (12-i) comprises a forcible change signal generating means for generating a forcible change signal (CG n ); and each of said pixel data arbitration circuits (15-i) comprises: first comparing means (181) for detecting a coincidence between said group number (GN n-1 ) generated from said outline generating means (10) and a group number (GN n ) stored in the corresponding frame memory control means (12-n); second comparing means (182) for detecting whether a priority number (PN n ) stored in the corresponding frame memory control means (12-n) is larger than a priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit (15-(n-1)); first selecting means (187) for outputting, when said forcible change signal (CG n ) is active, the group number (GN n ) stored in the corresponding frame memory control means (12-n), and for outputting, when said forcible change signal (CGn) is not active, said group number (GN n-1 ) generated from said outline generating means (10); second selecting means (186) for outputting, when said forcible change signal (CG n ) is active or when said first comparing means detects the coincidence and said second comparing means detects that the priority number (PN n ) stored in the corresponding frame memory control means (12-n) is larger than the priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit, the priority number (PN n ) and the pixel data (PD n ) stored in the corresponding frame memory control means (12-n), and for outputting, when said forcible change signal (CG n ) is not active and when said first comparing means does not detect a coincidence or when said second comparing means detects that the priority number (PN n ) stored in the corresponding frame memory control means (12-n) is smaller than the priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit, the priority number (PN n-1 ) and the pixel data (PD n-1 ) sent from the previous stage pixel data arbitration circuit.

Claim 18

A multiwindow display control apparatus as claimed in claim 17, wherein each of said frame memory control means (15-n) stores a display enable signal (DE n ) indicating whether or not each pixel is allowed to be displayed, and said first selecting means (187) and said second selecting means (186) select said group number (GN n ), said priority number (PN n ), and the pixel data (PD n ) stored in the corresponding frame memory control means (12-n) to be output to the next stage pixel data arbitration circuit (15-(n+1)) when said display enable signal (DE n ) indicates that the pixel is allowed to be displayed.

Claim 19

A multiwindow display control apparatus as claimed in any of claims 9 to 18, wherein said outline generating means (10) comprises: display enable region address generating means (91); group window rectangular region generating means (92), operatively connected to said display enable region address generating means (91), for generating group window rectangular region signals (GW#i) of said group of windows (GW); special region generating means (93) for generating special region signals; display priority sorting means (94), operatively connected to said group window region rectangular region generating means (92) and to said special region generating means (93), for sorting said group window rectangular region signals according to the desired order of the display priorities of said group of windows; display priority determining means (95), operatively connected to said display priority sorting means (94), for making only one of said group window rectangular region signals having the highest display priority enabled; and group number register means (96), operatively connected to said display priority determining means (95), for outputting a desired group number signal (GN) provided to said group window having the highest display priority.

Claim 20

A multiwindow display control apparatus as claimed in claim 19, wherein each of said group window rectangular region generating means (92) comprises: X start address detecting means (111, 115-1) for detecting an X start address of the corresponding group window; Y start address detecting means (112, 115-2) for detecting a Y start address of the corresponding group window; X end address detecting means (113, 115-3) for detecting an X end address of the corresponding group window; and Y end address detecting means (114, 115-4) for detecting a Y address of the corresponding group window.

Claim 21

A multiwindow display control apparatus as claimed in claim 19 or 20, wherein said special region generating means (93) comprises: change point coordinate storing memory (123) for storing change points between two of said group of windows to be displayed on the display enable region.

Claim 22

A multiwindow display control apparatus as claimed in claim 19, 20 or 21 wherein said pixel data arbitration means (14) comprises a plurality of pixel data arbitration circuits (15-i) respectively connected to said frame memory control means (12-i), said pixel data arbitration circuits (15-i) being connected to each other by a daisy chain structure.

Claim 23

A multiwindow display control apparatus as claimed in claim 22, wherein each of said pixel data arbitration circuits (15-i) comprises: first comparing means (192) for detecting a coincidence between said group number (GN n-1 ) generated from said outline generating means (10) and a group number (GN n ) stored in the corresponding frame memory control means (12-n); second comparing means (193) for detecting whether a priority number (PN n ) stored in the corresponding frame memory control means (12-n) is larger that a priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit (15-(n-1)); first selecting means (191) for selecting a group window rectangular region signal (GW n ) of the corresponding group of windows (GW) in response to said group number signal (GN n ) from the corresponding frame memory control means (12-i), said selected group window rectangular region signal (GW n ) being supplied to the corresponding frame memory control means (12-i) for determining the display position of the pixel data by relative coordinates with respect to said group window rectangular region signal; and second selecting means (208) for outputting, when said first comparing means detects the coincidence and said second comparing means detects that the priority number (PN n ) stored in the corresponding frame memory control means (12-n) is larger than the priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit, the priority number (PN n ) and the pixel data (PD n ) stored in the corresponding frame memory control means (12-n), and for outputting, when said first comparing means does not detect a coincidence or when said second comparing means detects that the priority number (PN n ) stored in the corresponding frame memory control means (12-n) is smaller than the priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit, the priority number (PN n-1 ) and the pixel data (PD n-1 ) sent from the previous stage pixel data arbitration circuit, said group number (GN n-1 ) generated from said outline generating means (10) being passed to the next stage pixel data arbitration circuit (15-(n+1)).

Claim 24

A multiwindow display control apparatus as claimed in claim 22 or 23, wherein each of said frame memory control means (15-n) stores a display enable signal (DE n ) indicating whether or not each pixel is allowed to be displayed, and said selecting means (154) selects said priority number (PN n ) and the pixel data (PD n ) stored in the corresponding frame memory control means (12-n) to be output to the next stage pixel data arbitration circuit (15-(n+1)) when said display enable signal (DE n ) indicates that the pixel is allowed to be displayed.

Claim 25

A multiwindow display control apparatus as claimed in any of claims 9 to 24, wherein each of said pixel data arbitration circuits (15-i) comprises: first selecting means (201) for selecting a group window rectangular region signal (GW n ) of the corresponding group window (GW) in response to said group number signal (GN n ) from the corresponding frame memory control means (12-i), said selected group window rectangular region signal (GW n ) being supplied to the corresponding frame memory control means (12-i) for determining the display position of the pixel data by relative coordinates with respect to said group window rectangular region signal; and first comparing means (202) for detecting a coincidence between said group number (GN n-1 ) generated from said outline generating means (10) and a group number (GN n ) stored in the corresponding frame memory control means (12-n); second comparing means (203) for detecting whether a priority number (PN n ) stored in the corresponding frame memory control means (12-n) is larger that a priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit (15-(n-1)); second selecting means (208) for outputting, when said first comparing means detects the coincidence and said second comparing means detects that the priority number (PN n ) stored in the corresponding frame memory control means (12-n) is larger than the priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit, the priority number (PN n ) in the corresponding frame memory control means (12-n), and for outputting, when said first comparing means does not detect the coincidence or when said second comparing means detects that the priority number (PN n ) stored in the corresponding frame memory control means (12-n) is smaller than the priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit, the priority number (PN n-1 ) sent from the previous stage pixel data arbitration circuit; third comparing means (204) for detecting a coincidence between the priority number (PN n-1 ) sent from the previous stage pixel data arbitration circuit (15-(n-1)) and the priority number (PN n ) stored in the corresponding frame memory control means (12-n); and pixel data calculating means (207) for outputting, when said first comparing means detects the coincidence and said second comparing means detects that the priority number (PN n ) stored in the corresponding frame memory control means (12-n) is larger than the priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit, the pixel data (PD n ) in the corresponding frame memory control means (12-n); for outputting, when said first comparing means does not detect the coincidence or when said second comparing means detects that the priority number (PN n ) stored in the corresponding frame memory control means (12-n) is smaller than the priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit, the pixel data (PD n-1 ) sent from the previous stage pixel data arbitration circuit; and for performing, when said first comparing means and said third comparing means respectively detect the coincidences, a predetermined calculation between said pixel data (PD n-1 ) sent from the previous stage pixel data arbitration circuit (15-(n-1)) and said pixel data (PD n ) in the corresponding frame memory control means (12-n), and for outputting the calculated result; said group number (GN n-1 ) generated from said outline generating means (10) being passed to the next stage pixel data arbitration circuit (15-(n+1)).

Claim 26

A multiwindow display control apparatus as claimed in claim 25, wherein each of said frame memory control means (15-n) stores a display enable signal (DE n ) indicating whether or not each pixel is allowed to be displayed; said second selecting means (208) selecting said priority number (PN n ) stored in the corresponding frame memory control means (12-n) to be output to the next stage pixel data arbitration circuit (15-(n+1)) when said display enable signal (DE n ) indicates that the pixel is allowed to be displayed; and said pixel data calculating means (207) outputting said pixel data (PD n ) stored in the corresponding frame memory control means (15-n) or performing said predetermined calculation when said display enable signal (DE n ) indicates that the pixel is allowed to be displayed.

Claim 27

A multiwindow display control apparatus as claimed in any of claims 9 to 26, wherein: each of said frame memory control means (12-i) comprises forcible change signal generating means for generating a forcible change signal (CG n ); and each of said pixel data arbitration circuits (15-i) comprises: first selecting means (211) for selecting a group window rectangular region signal (GW n ) of the corresponding group of windows (GW) in response to said group number signal (GN n ) from the corresponding frame memory control means (12-i), said selected group window rectangular region signal (GW n ) being supplied to the corresponding frame memory control means (12-i) for determining the display position of the pixel data by relative coordinates with respect to said group window rectangular region signal; first comparing means (212) for detecting a coincidence between said group number (GN n-1 ) generated from said outline generating means (10) and a group number (GN n ) stored in the corresponding frame memory control means (12-n); second comparing means (213) for detecting whether a priority number (PN n ) stored in the corresponding frame memory control means (12-n) is larger than a priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit (15-(n-1)); second selecting means (218) for outputting, when said forcible change signal (CG n ) is active, the group number (GN n ) stored in the corresponding frame memory control means (12-n), and for outputting, when said forcible change signal (CG n ) is not active, said group number (GN n-1 ) generated from said outline generating means (10); and third selecting means (217) for outputting, when said forcible change signal (CG n ) is active or when said first comparing means detects a coincidence and said second comparing means detects that the priority number (PN n ) stored in the corresponding frame memory control means (12-n) is larger than the priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit, the priority number (PN n ) and the pixel data (PD n ) stored in the corresponding frame memory control means (12-n), and for outputting, when said forcible change signal (CG n ) is not active and when said first comparing means does not detect a coincidence or when said second comparing means detects that the priority number (PN n ) stored in the corresponding frame memory control means (12-n) is smaller than the priority number (PD n-1 ) sent from the previous stage pixel data arbitration circuit, the priority number (PN n-1 ) and the pixel data (PD n-1 ) sent from the previous stage pixel data arbitration circuit.

Claim 28

A multiwindow display control apparatus as claimed in claim 27, wherein each of said frame memory control means (15-n) stores a display enable signal (DE n ) indicating whether or not each pixel is allowed to be displayed, and said first selecting means (187) and said third selecting means (217) select said group number (GN n ), said priority number (PN n ), and the pixel data (PD n ) stored in the corresponding frame memory control means (12-n) to be output to the next stage pixel data arbitration circuit (15-(n+1)) when said display enable signal (DE n ) indicates that the pixel is allowed to be displayed.

Claim 29

A multiwindow display control apparatus as claimed in any of claims 9 to 28, characterized in that: said pixel data arbitration unit (14) comprises a plurality of pixel data arbitration circuit (15-i) corresponding to said respective frame memory control unit (12-i), the connections of at least the group number signal line, the priority number signal line, and the pixel data signal line in the signal lines among the pixel data arbitration circuits, are bus connections among the respective pixel data arbitration circuits.