← Back to Patent Explorer
EP0461631A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Data storing device having a plurality of registers allotted for one address

Assignee: Toshiba Corp
•
Filing: 1991-06-12
•
Granted: —
•
Expires: 2011-06-12
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A data storing device has at least first to third registers (R1, R1' and R2). When the first register (R1) is accessed, the second register (R1') is set into an accessible state in a preset cycle succeeding to a cycle in which the first register (R1) is accessed. The same address as that of the second register (R1') is assigned to the third register (R2) and access to the third register (R2) is inhibited in a preset cycle in which the second register (R1') is accessed. An access control circuit (14, 15, 16, 17) controls permission/inhibition of access to the second and third registers (R1' and R2).

Inventors

  • 👤 Kazuyoshi c/o Intellectual Pty Division Yoshida

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-02 16:10
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/063

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 169 words
A data storing device having a plurality of data holding means to which respective addresses are assigned and permitting data to be read out from the data holding means designated by a selected address, characterized in that said plurality of data holding means include first data holding means (R1) for holding data; second data holding means (R1') set into an accessible state in a preset cycle succeeding to a cycle in which said first data holding means (R1) is accessed; third data holding means (R2) having the same address as that of said second data holding means (R1') allotted thereto and set into an access inhibition state in a preset cycle in which said second data holding means (R1') is accessed; and one of said second and third data holding means (R1' and R2) to which the same address is assigned is selected by controlling permission/inhibition of access to said second and third data holding means (R1' and R2) by use of access control means (14, 15, 16, 17).
Claim 2
Dependent Claim 52 words
A data storing device according to claim 1, characterized in that a first address (A1) is assigned to said first data holding means (R1) and a second address (A2) which is higher than the first address (A1) by one is assigned to said second and third data holding means (R1' and R2).
Claim 3
Dependent Claim 38 words
A data storing device according to claim 1, characterized in that said first, second and third data holding means (R1, R1' and R2) are used as I/O registers of a single-chip microcomputer and formed in the same chip.
Claim 4
Dependent Claim 40 words
A data storing device according to claim 1, characterized by further comprising decoder means (12) for receiving an address signal (AD) and decoding the address signal (AD) to select said first to third data holding means (R1, R1' and R2).
Claim 5
Dependent Claim 69 words
A data storing device according to claim 4, characterized in that said access control means includes an access control section (14) for receiving an output of said decoder means (12); and logic gate means (15, 16, 17) for selecting one of said second and third data holding means (R1' and R2) according to an output of said decoder means (12) and an output of said access control section (14).
Claim 6
Dependent Claim 114 words
A data storing device according to claim 5, characterized in that said logic gate means includes a first AND gate (16) for receiving an output of said decoder means (12) at one input terminal and receiving an output signal (AC2) of said access control section (14) at the other input terminal and supplying an output to said second data holding means (R1'); and a second AND gate (15) for receiving an output of said decoder means (12) at one input terminal and receiving an inverted signal (AC1) of the output signal (AC2) of said access control section (14) at the other input terminal and supplying an output to said third data holding means (R2).

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag