EP0460853A2
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EP
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Memory system
Assignee: NCR International Inc
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Filing: 1991-05-28
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Granted: —
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Expires: 2011-05-28
Abstract
Abstract A memory system comprises a memory (12) for transferring m data bytes (e.g. 16 bytes) at a time, first and second buses (A,B) each having widths (e.g. 4 bytes) of less than m data bytes, first parallel m-byte wide read and write registers (16,18) connected between the first bus (A) and the memory (12) and second parallel m-byte wide read and write registers (20,22) connected between the second bus (B) and the memory (12). With this arrangement data can be transferred m bytes at a time to and from the memory (12), with transfer between the read and write registers and the associated buses (A,B) taking place independently of memory transfer, and with a number of bytes corresponding to the associated bus width.
Inventors
- 👤 William J. Kass
- 👤 Michael R. Hilley
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 15:13
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4009; G06F13/4018
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
145 words
A memory system, including a memory (12) adapted to store m data bytes at each addressable location therein, and first (A) and second (B) data buses arranged to transfer data to and from said memory (12), characterized in that said first and second data buses (A,B) have respective widths of n bytes and p bytes, where n and p are both less than m, in that m byte-wide first write registers (16a-16p) are connected in parallel between said first bus (A) and said memory (12), in that m byte-wide first read registers (18a-18p) are connected in parallel between said first bus (A) and said memory (12), in that m byte-wide second write registers (20a-20p) are connected between said second bus (B) and said memory (12), and in that m byte-wide second read registers (22a-22p) are connected between said second bus (B) and said memory (12).
Claim 2
Dependent Claim
117 words
A memory system according to claim 1, characterized by a first address line (WORD ADD A) connected to each of said first write registers (16a-16p), n first control lines (A BYTE EN), each connected to selected ones of said first write registers (16a-16p), a second address line (WORD ADD B) connected to each of said second write registers (20a-20p), arid p second control lines (B BYTE EN) each connected to selected ones of said second write register (20a-20p), whereby said first and second address line (WORD ADD A, WORD ADD B) provide signals which selectively enable said first and second write registers (16a-16p, 20a-20p) to receive one or more data bytes from the associated data bus (A,B).
Claim 3
Dependent Claim
59 words
A memory system according to claim 2, characterized by multiplexing means (36a-36p, 38a-38p), connected between said first and second write registers (16a-16p, 20a-20p) and said memory (12), and responsive to control signals (A/B, WRITE ENABLE) to selectively enable the transfer of up to m data bytes from said first or second write registers (16a-16p, 20a-20p) into said memory (12).
Claim 4
Dependent Claim
58 words
A memory system according to claim 2 or claim 3, characterized by third and fourth control lines (A/B, DATA LAT), connected respectively to each said first read register (18a-18p) and each said second read register (22a-22p) whereby said first or second read register (18a-18p, 22a-22p) are enabled to receive and latch m data bytes from said memory (12).
Claim 5
Dependent Claim
74 words
A memory system according to claim 4, characterized by n first multiplexers (40a-40d) and p second multiplexers (44a-44d) connected between said first and second read registers (18a-18p, 22a-22p) and said first and second buses (A,B) respectively, whereby a selected group of n of said first read registers (18a-18p) and/or a selected group of p of said second read registers (22a-22p) provides data signals to said first bus (A) and/or said second bus (B), respectively.
Claim 6
Dependent Claim
39 words
A memory system according to claim 5, characterized in that said first address line (WORD ADD A) is connected to said first multiplexers (40a-40d) and said second address line (WORD ADD B) is connected to said second multiplexers (44a-44d).
Claim 7
Dependent Claim
22 words
A memory system according to any one of the preceding claims, characterized in that n and p are integer divisors of m.
Claim 8
Dependent Claim
17 words
A memory system according to any one of the preceding claims, characterized in that n = p.
References Cited (Backward Citations)
No citation records indexed.
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