EP0459794A2
Expired / Lapsed
EP
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Read only memory device
Assignee: NEC Corp
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Filing: 1991-05-30
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Granted: —
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Expires: 2011-05-30
Abstract
Abstract An electrically programmable read only memory device is equipped with a plurality of write-in circuits (WR11 to WR18) for concurrently writing a plurality of data bits into memory cells (M11 to Mmn; MBL12 to MBL18), wherein a write-in controlling unit (15) sequentially produces a plurality of write-in controlling signals (WCL1/WCL2) supplied to a transfer gate groups for sequentially transferring the data bits to column selectors (CSL11 to CSL18) respectively associated with memory cell blocks (MBL11 to MBL18) so that the peak current in the write-in operation is not increased together with the number of the data bits concurrently written into the memory cells.
Inventors
- 👤 Misao Higuchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 04:10
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C17/00; G11C17/14; G11C17/18
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
280 words
A non-volatile programmable read only memory device comprising a) a plurality of memory cells (M11 to Mmn) arranged in rows and columns and divided into a plurality of memory cell blocks (MBL11 to MBL18) each including columns of said memory cells selected from said columns of said memory cells, b) a plurality of word lines (W1 to Wm) coupled to said rows of said memory cells and driven for selecting one of said rows of said memory cells, c) a plurality of column selectors (CSL11 to CSL18) respectively associated with said memory cell blocks, each of said column selectors being responsive to a column selecting signal (SL11 to SL1n) for selecting a column of said memory cells from said associated memory cell block, d) a plurality of data latching circuits (LT11 to LT18) for storing a plurality of write-in data bits, respectively, and e) a plurality of write-in circuits (WR11 to WR18; WR41 to WR44) associated with said plurality of data latching circuits and respectively producing a plurality of write-in signals indicative of said respective write-in data bits, said plurality of write-in signals being supplied to said column selectors, respectively, characterized by f) a write-in controlling unit (15) responsive to an external controlling signal (PGM) and sequentially producing a plurality of write-in controlling signal (WCL1/WCL2), and g) a transfer gate array (14; 41) having a plurality of transfer transistors (Qn51 to Qn58) divided into a plurality of transfer gate groups, and in that said transfer gate groups are respectively responsive to said plurality of write-in controlling signals for sequentially transferring said write-in data bits to said plurality of write-in circuits or said write-in signals to said plurality of column selectors.
Claim 2
Dependent Claim
44 words
A non-volatile programmable read only memory device as set forth in claim 1, in which said write-in circuits (WR11 to WR18) are coupled between said latching circuits (LT11 to LT18) and said transfer gate array (14), said transfer gate array propagating said write-in signals.
Claim 3
Dependent Claim
26 words
A non-volatile programmable read only memory device as set forth in claim 2, in which said write-in controlling signal (WCL1/WCl2) are partially overlapped with each other.
Claim 4
Dependent Claim
82 words
A non-volatile programmable read only memory device as set forth in claim 3, in which said non-volatile programmable read only memory device further comprises a shifting unit (13) coupled between said transfer gate array (14) and said column selectors (CSL11 to CSL18), said shifting unit being operative to propagate said write-in signals to said column selectors, respectively, in a programming mode, said shifting unit being further operative to transfer data bits from one of said column selectors to a sense amplifier circuit.
Claim 5
Dependent Claim
100 words
A non-volatile programmable read only memory device as set forth in claim 1, in which said transfer gate array (41) is coupled between said latching circuits (LT11 to LT18) and said write-in circuits (WR41 to WR44) for selectively propagating said write-in data bits, said latching circuits being divided into a plurality of latching circuit groups respectively connectable through said plurality of transfer gate groups to said write-in circuits, each of said write-in circuits having a plurality of output nodes so as to sequentially supplying said write-in signals indicative of said write-in data bits sequentially fed from said associated latching circuits.
Claim 6
Dependent Claim
33 words
A non-volatile programming read only memory device as set forth in claim 5, in which said second write-in controlling signal (WCL2) takes place immediately after said first write-in controlling signal (WCL1) is removed.
Claim 7
Dependent Claim
85 words
A non-volatile programmable read only memory device as set forth in claim 5, in which said non-volatile programmable read only memory device further comprises a shifting unit (13) coupled between said write-in circuits (WR41 to WR44) and said column selectors (CSL11 to CSL18), said shifting unit being operative to propagate said write-in signals to said column selectors, respectively, in a programming mode, said shifting unit being further operative to transfer data bits read out from one of said column selectors to a sense amplifier circuit.
References Cited (Backward Citations)
No citation records indexed.
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