EP0458693A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Document data input system for a scanner
Assignee: LG Electronics Inc
•
Filing: 1991-05-21
•
Granted: —
•
Expires: 2011-05-21
Abstract
Abstract A document data input system for a scanner capable of storing scanner data to another buffer memory of a microprocessor when applying the scanned data to a host computer. The document data input system comprising a host computer for storing scanned data to its internal hard disk, a scanner for scanning the document data, a scanner interface unit for interfacing between the host computer and the scanner, a microprocessor associated with a global memory and a local memory, and an interface unit for latching the data from the scanner interface unit and applying the data to the microprocessor, and applying a completion signal to the scanner interface unit when the data input to the microprocessor is completed. The system provides the enhanced reliability and the using efficiency and is capable of being used for the document recognition system comprising a multiprocessor.
Inventors
- 👤 Mun Hyoung Cho
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 16:45
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/00127; H04N1/00204; H04N1/00236; H04N1/00241; G; G06; G06F; G06F13/00; G06F13/38; G06F13/382; G06F13/385; H04N1/32; H04N1/32561; H04N2201/00; H04N2201/0008; H04N2201/0034; H04N2201/0077; H04N2201/0081
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
129 words
A document data input system for a scanner, comprising; a host computer for controlling the whole operation of the system and receiving and storing scanned data to a hard disk; a scanner for scanning document data; a scanner interface unit for carrying out a data interface operation between the host computer and the scanner, upon the control of the host computer; a microprocessor associated with a global memory and a local memory; an d an interface unit for latching the scanned data passed through the scanner interface unit upon the control of the host computer and applying the latched data to the microprocessor upon the control of the microprocessor and then applying a completion signal to the scanner interface unit when the data input to the microprocessor is completed.
Claim 2
Dependent Claim
290 words
The document data input system for a scanner as claimed in claim 1, wherein the scanner interface unit is constituted such that data ports D₀-D₇, read control signal port IOR , write control signal port IWO , selection signal ports SA₀ and SA₁, and reset signal port RSD of the host computer are connected respectively to data ports D₀-D₇, read port RD , write port WR , selection ports A₀ and A₁, and reset port RS of a scanner interface and also input/output signal ports IO₀-IO₃ of the host computer are connected to a chip selection port CS of the scanner interface via an AND gate , output ports PA₀-PA₇ of the scanner interface are connected via a buffer to data ports D₁-D₈ of the scanner together with the input ports PB₀-PB₇ thereof, to the data ports D₁-D₈ of the scanner; a mode control signal port PC₄ of the scanner interface is connected to a preset/scanner port PR/ SC of the scanner and an enable port 2G of a multiplexer as well as to an enable port G of the buffer and an enable port 1G of the multiplexer via an inverter; interrupt signal port PC₃, acknowledge port PC₆, and output buffer full port PC₇ of the scanner interface are connected to ports 1A₃, 1Y₂ and 1A₁ of the multiplexer, input buffer full port IC₁ via an OR gate to a port 2A₃ of the multiplexer, and also ports 1Y₃ and 2Y₃, 1A₂ and 1Y₁ to ports BY, RS and ST of the scanner ; and then the port ST of the scanner is connected to a port 2A₂ of the multiplexer and also the port 2Y₂ via an OR gate to a strobe port PC₂ of the scanner interface.
Claim 3
Dependent Claim
183 words
The document data input system for a scanner as claimed in claim 1, wherein the interface unit is constituted such that data ports D₀-D₇ of the host computer are connected to data ports D₀-D₇ of the latch, a reset signal port RSD of the host computer is connected via an inverter to a preset port PS of the first flip-flop and to a clear port CL of the second flip-flop, an input/ouput port IO₁ of the host computer is connected to a clock port CK of the latch, a clear port CL of the first flip-flop, and a preset port PS of the second flip-flop, an output port Q of the first flip-flop is connected to an interrupt port INT of the microprocessor, an output demand signal port P₆ and data ports D₀-d₇ of the microprocessor are connected respectively to an output enable port OE and output ports Q₀-Q₇ of the latch, and an interrupt acknowledge signal port IACK and a completion signal port P₅ of the microprocessor are connected respectively to clock ports CK and CK of the first and second flip-flops.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.