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EP0458614A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Memory device with standby function

Assignee: NEC Corp
•
Filing: 1991-05-22
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Granted: —
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Expires: 2011-05-22
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Abstract

Abstract A memory device includes a memory (101-2), an address latch (101-6), a built-in incrementer (101-5), and an address decoder (101-4). The address decoder (101-4) has a mapping register (201) which assigns the memory (101-2 ) to a prede termined address. The address decoder (101-4) further includes a standby signal producer (300) which detects whether or not the address latch (101-6) addresses an address specified by the mapping register (201) and which sets the memory device to a standby state of a low power consumption when such is not detected. The memory device can be set to a standby state even when the memory device is connected to a microcomputer with a protocol by which an address of the memory is not outputted each time. This arrangement enables to save power consumption of the computer, to decrease the load of a power supply circuit in a microcomputer (100) applied apparatus and to make the apparatus compact.

Inventors

  • 👤 Osamu Matsushima

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-04 10:39
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3206; G06F1/3215; G06F1/3234; G06F1/325; G06F1/3275; Y; Y02; Y02D; Y02D10/00

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 116 words
A memory device in which a memory means (101-2), an address means (101-6) having an increment means (101-5) and an address decoding means (101-4) are installed on the same semiconductor substrate, said address decoding means (101-4) characterized by comprising:- a mapping means (201) which assigns said memory means (101-2) to a predetermined address; and a standby means (300) which detects whether said address means (101-6) is specifying an address assigned by said mapping means (201) and which outputs a standby signal (101-41) to set said memory device to a standby state of low power consumption when said standby means (300) does not detect said address means (101-6) specifying said address assigned by said mapping means (201).
Claim 2
Dependent Claim 95 words
A memory device according to claim 1, in which said mapping means (201) includes memory addressing registers (201-1,201-2) and said standby means (300) includes a standby signal inverter (203) and incremental output inverters (205,206), AND gates (207 - 210) and transfer gates (204-1 - 204-4), and a 2-4 decoder (202) which decodes outputs of said memory addressing registers (201-1,201-2) and whose outputs are connected to said transfer gates (204-1 - 204-4) for selecting outputs of said AND gates (207 - 210) in order to output said standby signal (101-41) through said standby signal inverter (203).
Claim 3
Dependent Claim 37 words
A memory device according to claim 1, which includes a bus control circuit (101-1) and a sense amplifier (101-3) which are set to a standby state by said standby signal (101-41) produced by said standby means (300).
Claim 4
Dependent Claim 34 words
A memory device according to claim 1, which further comprises a chip enable terminal (CE) through which an external circuit (402) can set said memory device to a standby state of low power consumption.
Claim 5
Dependent Claim 63 words
A memory device according to claim 4, which further comprises an inverter (401-1) to which is inputted a signal of said chip enable terminal (CE), and an OR gate (401-2) to which both an output signal of said inverter (401-1) and said standby signal (101-41) are inputted and which outputs a logical OR signal to set said memory device to a standby state.

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