EP0458516A2
Expired / Lapsed
EP
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Memory access bus arrangement
Assignee: AT&T Inc
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Filing: 1991-05-15
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Granted: —
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Expires: 2011-05-15
Abstract
Abstract Bus arrangements are disclosed for interconnecting processors (P1-P8) and main memory modules (M1-M9) of a shared memory multiprocessor system. A single address bus (120) interconnects all processors and memory modules, but odd and even memory modules communicate data to and from the processors via an odd (131) and an even (133) data bus. Each memory reading occupies four bus cycles on one of the data buses. On the address bus, two of each four cycles are available for addressing odd and even memory modules, and the other two are available for sending invalidation addresses among the caches (147) of the processors. The single address bus is used for transmitting a relatively narrow (32-bit) address word throughout the system, one address on each bus cycle, while the data buses are time shared to transmit a wide data word (256-bit) in four bus cycles, and each data bus is only connected to half the main memory modules. Such an arrangement makes excellent use of limited bus resources to transmit information where needed and when needed.
Inventors
- 👤 Subhasis Laha
- 👤 Dennis Joseph Thompson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 15:05
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/1652; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
165 words
A multiprocessor system comprising a plurality of processor means (P1-P8) for processing data, a plurality of main memory modules (M1-M4), and bus means (120,122,131,133) for interconnecting said processors and said memory modules, CHARACTERISED IN THAT the bus means comprises a time-shared address bus (120) for transmitting a plurality of addresses in a plurality of time intervals, connected to all of said processor means and all of said memory modules, and a plurality of data buses (131,133), each of said data buses being connected to a subset of less than all of said memory modules and to all of said processor means, and wherein, in operation, a first memory module connected to a first of said data buses and a second memory module connected to a second of said data buses receive addresses during different time intervals from said time shared address bus, and each responds with data stored at one of said addresses in an overlapping fashion over said first and said second data buses.
Claim 2
Dependent Claim
54 words
A system as claimed in claim 1 wherein each of said processor means comprises cache memory means (147) for storing data and corresponding addresses, wherein, in operation, addresses on said address bus are transmitted to said processor means for checking against said corresponding addresses of data stored in each said processor cache memory means.
Claim 3
Dependent Claim
54 words
A system as claimed in claim 2 comprising a snoop bus (122) connected to each of said processor means for conveying signals indicating that one of said processor means has detected a match between an address on said address bus and an address of data stored in cache means of said one processor means.
Claim 4
Dependent Claim
32 words
A system as claimed in claim 3 wherein said signals convey data characterising the state of data associated with said address of data stored in cache means of said one processor means.
Claim 5
Dependent Claim
41 words
A system as claimed in claim 4 wherein, for one of said states, said one processor means serves to provide data in its cache means to one of said data buses in substitution for data from one of said memory modules.
Claim 6
Dependent Claim
33 words
A system as claimed in claim 5 wherein, for said one of said states, said one processor means serves to provide data in its cache means to said one of said memory modules.
Claim 7
Independent Claim
43 words
A system as claimed in any one of claims 2 to 6 wherein a MESI (Modified, Exclusive, Shared, Invalid) protocol is used for cache coherency among said cache means, and wherein said address bus serves to transmit invalidation addresses among said processor means.
Claim 8
Independent Claim
24 words
A system as claimed in any preceding claim wherein different ones of said data buses are connected to disjoint subsets of said memory modules.
Claim 9
Independent Claim
56 words
A system as claimed in any preceding claim wherein, in operation, each of said data buses carries read-out signals from any of ones of said memory modules to any of said plurality of processor means, and carries write signals from any of said plurality of processor means to any of said ones of said memory modules.
Claim 10
Independent Claim
22 words
A system as claimed in any preceding claim wherein, in operation, access to said addressing bus is allocated by arbitration means (141,142,145).
Claim 11
Dependent Claim
23 words
A system as claimed in claim 10 wherein said arbitration means comprises a global arbiter (141,142) and a plurality of distributed arbiters (145).
Claim 12
Dependent Claim
30 words
A system as claimed in claim 11 wherein, in operation, all processor means which request access to said addressing bus during one arbitration cycle are served once during said cycle.
Claim 13
Dependent Claim
20 words
A system as claimed in claim 10 comprising an arbitration bus (143,144) for distributing arbitration information among the processor means.
Claim 14
Dependent Claim
46 words
A system as claimed in claim 13 wherein said arbitration means comprises a global arbiter (141,142) and a plurality of local arbiters (145), each associated with a processor means, and wherein said arbitration bus serves to transmit signals between said global arbiter and said local arbiters.
Claim 15
Dependent Claim
39 words
A system as claimed in claim 14 wherein, in operation, each local arbiter receives signals from said global arbiter and other local arbiters for determining whether its associated processor means can transmit an address at a next time interval.
Claim 16
Dependent Claim
20 words
A system as claimed in claim 1 wherein, in operation, said address bus conveys invalidation addresses among said processor means.
Claim 17
Dependent Claim
59 words
A system as claimed in claim 16 wherein said time-shared address bus can transmit one address during a time slot, and wherein said address bus is available for transmitting addresses for said memory modules during ones of a fixed portion of the time slots, and is available for transmitting invalidation addresses whenever memory module addresses are not being transmitted.
Claim 18
Dependent Claim
42 words
A system as claimed in claim 1 wherein one of said processor means comprises a peripheral memory controller for controlling a peripheral memory, and said one processor means serves to transmit invalidation signals when main memory is updated from said peripheral memory.
Claim 19
Dependent Claim
92 words
A system as claimed in claim 1 wherein each of said address and data buses is time shared such that signals are transmittable in consecutive time slots of each of said buses, each of said main memory modules serves to transmit data, corresponding to an address received over said address bus in one time slot, over one of said first and said second data buses in four consecutive time slots of said one data bus, and data is transmittable concurrently in corresponding time slots over said first and said second data buses.
Claim 20
Dependent Claim
35 words
A system as claimed in claim 19 wherein each processor means is controlled by a clock, and each time slot of one of said buses is a multiple of a cycle time of said clock.
Claim 21
Dependent Claim
50 words
A system as claimed in claim 1 wherein said address bus serves to convey a plurality of time multiplexed addresses for each data transfer cycle from one of said memory modules, said data transfer cycle corresponding to a transmission of data for one of said plurality of time multiplexed address.
Claim 22
Dependent Claim
444 words
A multiprocessor system comprising a first plurality of processor means (P1-P8) for processing data, a second plurality of main memory modules (M1-M4), and bus means (120,122,131,133) for interconnecting said processor means and said memory modules, CHARACTERISED IN THAT the bus means comprises an addressing bus (120) connected to all of said processor means and all of said memory modules, and a plurality of data buses (131,133), each of said data buses being connected to a proper subset of said memory modules and to all of said processor means, wherein said address bus serves to convey invalidation addresses among said processor means, said address bus is time-shared and can transmit one address during a time slot, and said address bus serves to address said memory modules during ones of a first half of the time slots and to convey said invalidation addresses during ones of a second half of said time slots; each of said processor means comprises cache memory means (147) for storing data and corresponding addresses, wherein, in operation, addresses on said address bus are transmitted to said processor means for checking against said corresponding addresses of data stored in each said processor cache memory means; and there is provided a snoop bus (122) connected to each of said processor means for conveying signals, said signals conveying data characterising a state of data associated with a corresponding address of data stored in cache means of one of said processor means indicating that said one processor means has detected a match between an address on said address bus and an address of data stored in cache means of said one processor means, wherein, for one of said states, said one processor means serves to provide data in its cache means to one of said data buses and to one of said memory modules in substitution for data from one of said memory modules; and wherein: said address bus serves to convey a plurality of time multiplexed addresses for each data transfer cycle from one of said memory modules, said data transfer cycle corresponding to a transmission of data for one of said plurality of time multiplexed address; access to said addressing bus is allocated by arbitration means, comprising a global arbiter (141,142) and a plurality of distributed arbiters (145), all processor means which request access to said addressing bus during one arbitration cycle being, in operation, served for a first request before any processor means is served for a second request; and one of said processor means comprises a peripheral memory controller for controlling a peripheral memory, said one processor serving to transmit invalidation signals when main memory is updated from said peripheral memory.
References Cited (Backward Citations)
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