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EP0458438A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Data element switch

Assignee: Telent Technologies Services Ltd
•
Filing: 1991-02-22
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Granted: —
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Expires: 2011-02-22
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Abstract

Abstract The invention concerns an Asynchronous Transfer Mode Switch having a plurality of input stages (IS1 ... ISN) each for receiving a digital data transmission stream (DS1 ...256) consisting of a series of cells and wherein each input stage of the switch includes a circuit (52) for determining the destination of the cells of that data stream, and a circuit (63) for disassembling each cell into cell elements and for allocating to each cell element routing data to enable it to be routed across the central stages. <IMAGE>

Inventors

  • 👤 Richard John Proctor
  • 👤 Mark Timothy Jeffrey
  • 👤 Thomas Slade Maddern
  • 👤 Alexander Schroder Philip

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-02 21:04
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H03; H03K; H03K17/00; G; G02; G02F; G02F1/00; G02F1/29; G02F1/295; H04L49/00; H04L49/15; H04L49/1515; H04L49/153; H04L49/1538; H04L49/1553; H04L49/25; H04L49/253; H04L49/255; H04L2012/5638; H04L2012/5646; H04L2012/5647; H04L2012/565; H04L2012/5672; H04L2012/5678; H04L2012/5681

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 301 words
An Asynchronous Transfer Mode Switch having a plurality of input stages (IS1 ... ISN) each for receiving a digital data transmission stream (DS1 ... 256) consisting of a series of cells, a cell comprising data and a header containing control data from which the destination of the cell can be determined, a plurality of central stages (41) connected to the input stages to receive the data from the input stages to be switched across the switch, and a plurality of output stages (OS1 ... OSN) each connected to the central stages, and wherein for every input stage there is a route to every central stage for the transmission of data, and from every central stage there is a route to every output stage, and wherein each input stage includes a circuit (52) for determining the destination of the cells of that data stream, and characterised in that the switch includes a circuit (63) for disassembling each cell into cell elements and for allocating to each cell element routing data to enable it to be routed across the central stages, means (54) for storing the cell elements in series, means (56) for requesting from a central stage permission to transmit a cell element in the series and after a predetermined delay a further request for the same destination point provided that the stored cell elements are derived from the same cell, means (56) for receiving a response from the central stage as to the availability of the requested destination between the sending of requests so that the sequence of sending a request for one cell element is interleaved with the response to the request for the preceding cell element, and means for transmitting each cell element to the central stage after a second predetermined delay from the receipt of a positive request.
Claim 2
Dependent Claim 91 words
A switch as claimed in Claim 1 and characterised in that the means (54) for storing the cell elements comprise a plurality of element queues operative to store in parallel successive cell elements, each said element queue being connected to a plurality of parallel element sender circuits (55), the element sender circuits operating under the control of a pathfinder control circuit (56) which examines the routing information carried by each cell element and sends requests to the central switch for a number of data elements stored in each cell element queue.
Claim 3
Dependent Claim 40 words
A switch as claimed in Claim 2 and characterised in that each pathfinder control circuit (56) sends a series of spaced requests to the central stage, each request being for a window for a cell element in the element queue.
Claim 4
Dependent Claim 51 words
A switch as claimed in Claim 3 and further characterised in that to maintain cell sequence integrity across the switch the input and output central stage access times are rotated in steps so that for any cell input to the switch there is a constant storage delay in the central stage.

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