EP0457310A2
Expired / Lapsed
EP
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Memory card
Assignee: Seiko Epson Corp
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Filing: 1991-05-15
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Granted: —
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Expires: 2011-05-15
Abstract
Abstract In a memory card (14) containing a DRAM (102) control means are provided to perform refresh control inside the memory card in response to an optimum refresh signal, and to separate the read-write operation and refresh operation to reduce the external access time to the memory card and improve the compatibility of the memory card. A value set in a setting circuit for the refresh time of the DRAM on the memory card and the value obtained by a counter circuit (3) counting clock pulses generated from an oscillation source (1) in the memory card are compared by a comparator circuit (5). When the above values are the same, a refresh signal is output and the DRAM (102) is refreshed. When the signals compared by the comparator circuit (5) are not the same, a refresh signal is not output, and read-write operation of the DRAM 102 is performed.
Inventors
- 👤 Noriaki Sakurada
- 👤 Fujikazu Sugimoto
- 👤 Ichiro Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 14:27
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G06K; G06K19/00; G06K19/06; G06K19/067; G06K19/07; G11C11/403
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
69 words
A memory card containing a DRAM (102) requiring refresh operation and a plurality of logic elements, which performs refresh operations and read-write operations according to external commands, wherein the memory card comprises: oscillation means (1) generating a clock pulse in the memory card; and refresh control means (6, 7) performing refresh operations automatically based on the clock pulse generated from the oscillation means and independent of external refresh operations.
Claim 2
Dependent Claim
218 words
A memory card according to claim 1, wherein said refresh control means comprises: a refresh signal generation circuit (27) that generates a refresh control signal (35) based on the clock pulse generated from the oscillation means (26); read-write control means (24, 25) that outputs the external address signal to the DRAM (102) while also generating the read or write control signal (34) for the memory card based on the external address signal and control signal; refresh/read-write operation setting means (29, 30, 31) that compares the count value of a counter (29) counting the clock pulses from the oscillation means (26) and a set value which determines the read-write operation period of the DRAM and outputs a refresh selection signal (36) when these values are the same and a read-write selection signal (36) when they are different; refresh/read-write selection means (28) that is responsive to the refresh selection and read-write selection signal and outputs the read or write control signal (34) from the read-write control means (24) to the DRAM when said values are different and outputs the refresh control signal (35) from the refresh signal generation circuit (27) to the DRAM when said values are the same, and identification means (32) that externally posts the refresh selection signal and read-write selection signal from the refresh/read-write operation setting means.
Claim 3
Dependent Claim
216 words
The memory card of claim 2 wherein the read-write control means comprises a read-write signal generation circuit (24), which generates the read-write control signal in response to the external address signal and control signal and outputs an enable signal, and a first multiplexer (25), which selects the external address signal in response to the enable signal and outputs it to the DRAM (102), the refresh/read-write operation setting means comprises a counter (29), which counts the clock pulses from the oscillation means (26), a read-write operation enable period setting circuit (31), in which the read-write period of the DRAM (102) is arbitrarily set, and a comparator circuit (30) , which compares the count value from the counter with the set value from the read-write operation enable period setting circuit; the refresh/read-write selection means comprises a second multiplexer (28), which selects one of the read-write operation control signal (34) from the read-write signal generation circuit and the refresh signal from the refresh signal generation circuit (27), and the identification means (32) comprises at least one register for storing the read-write selection signal and refresh selection signal from the comparator circuit (30), and a third multiplexer (33), which selects the read-write selection signal and refresh selection signal from the register or the memory data from or to the DRAM.
Claim 4
Dependent Claim
32 words
The memory card of claim 3 wherein a delay circuit (38) is inserted between the comparator circuit (30) and the second multiplexer (28) to delay the rise time of the refresh operation.
Claim 5
Dependent Claim
34 words
A memory card according to any of the preceding claims, wherein said refresh control means sets the DRAM (102) to a standby condition when it receives an external dummy signal during a refresh operation.
References Cited (Backward Citations)
No citation records indexed.
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