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EP0456394A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Video memory array having random and serial ports

Assignee: International Business Machines Corp
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Filing: 1991-04-26
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Granted: —
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Expires: 2011-04-26
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Abstract

Abstract An architecture for a memory array having a random access port and a serial access port configured and operable to provide selectively different ordering of the data bits at the two ports. The invention finds particular application in frame buffer VRAMs where video display pixel data is functionally replicated in the cells of the memory array. The pixel data at the serial access port is structured to coincide by row with the raster scan of the video display. On the other hand, addressing through the random access port provides pixel data for multiple rows, preferably in 2 x 2 pixel blocks, to improve rasterization processing efficiency for pattern variations projecting orthogonal to the scan orientation. The architecture is accomplished through the judicious sharing of column select functions and shift register arrangements. The invention is amenable to a mode select so as to provide conventional operation whereby both the random and serial ports communicate with analogous pixel data bit orders.

Inventors

  • 👤 Daryl John Kokoszka
  • 👤 Steven Philip Larky

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-29 23:14
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G06; G06T; G06T1/00; G06T1/60; H; H04; H04N; H04N19/00; H04N19/42; H04N19/423; H04N19/60; H04N19/61; G09G2360/00; G09G2360/12; G09G2360/126

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 121 words
A video random access memory (VRAM) for use with a pixel based video display configured as a plurality of rows and a plurality of columns of pixels, comprising: a memory array configured as a plurality of rows and a plurality of columns of data items; a random access data port; a serial access data port; means for accessing data representing a first plurality of pixels through the serial access port, the first plurality corresponding to pixels from a single display row in the pixel based display system; and means for accessing data representirLg a second plurality of pixels through the random access port, the second plurality corresponding to pixels from more than one display row in the pixel based display system.
Claim 2
Dependent Claim 36 words
A VRAM as claimed in claim 1, wherein the second plurality of pixels comprises an even number (y) of pixels, being y/2 pixels from a first display row and y/2 pixels from a second display row.
Claim 3
Dependent Claim 29 words
A VRAM as claimed in claim 2, wherein the first and second rows of pixels are adjacent, and the two sets of y/2 pixels are located in corresponding columns.
Claim 4
Dependent Claim 44 words
A VRAM as claimed in any preceding claim, in which there is a one-to-one correspondence between the pixel displayed at a particular row and column on the video display, and the data item stored at that row and column address in the memory array.
Claim 5
Dependent Claim 91 words
A VRAM as claimed in claim 4, further comprising: an address input port; and address decoding means responsive to an address placed on the address input port and operable such that when a particular row and column are selected, a) the first plurality of data items from the selected row are made available for access through the serial access data port; and b) the second plurality of data items, from the selected row and from at least one other row are made available for access through the random access data port.
Claim 6
Dependent Claim 47 words
A graphics adapter comprising: a VRAM as claimed in any preceding claim; logic means for writing pixel data to the VRAM random access data port; and logic means for reading pixel data from the VRAM serial access data port and transmitting the pixels to a video display.
Claim 7
Dependent Claim 56 words
A video display system comprising: a VRAM as claimed in any of claims 1 to 5; logic means for writing pixel data to the VRAM random access data port; a raster scanned video display; and logic means for reading pixel data from the VRAM serial access data port and displaying the pixels on the video display.

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