Adaptive channel impulse response estimation system using maximum likelihood sequence estimation

Claim 2

An adaptive MLSE apparatus using Viterbi algorithm and applicable to a digital data communication system which transmits data over a transmission channel, comprising: a matched filter to which a received signal and a predicted future channel impulse response are applied; a branchmetric compute circuit for calculating, in response to said predicted future channel impulse response and an output of said matched filter, a branchmetric of said received signal and outputting said branchmetric; an add, compare and select (ACS) circuit for estimating a maximum likelihood sequence (MLS) in response to an output of said branchmetric compute circuit, and outputting a result of estimation; a delay circuit for delaying said received signal by a demodulation time in which said result of estimation is outputted; a received signal regenerating filter for regenerating and outputting said received signal in response to an output of said ACS circuit; a filter control circuit for updating, in response to an output of said delay circuit, an output of said received signal regenerating filter, and internal states of said received signal regenerating filter, said internal states of said received signal regenerating filter such that a difference between said output of said delay circuit and said output of said received signal regenerating filter decreases; and channel impulse response predict circuit for predicting, in response to an output of said received signal regenerating filter control circuit and by using said output as a past change in said internal states of said received signal regenerating filter, a future path impulse response and outputting a result of prediction as said predicted future channel impulse response.

Claim 3

An adaptive channel impulse response estimation system for a digital data communication system which transmits data over a transmission channel, comprising: first internal state outputting means for generating, in response to a result of decision, a received signal and an estimated channel impulse response, a replica of said received signal and outputting first internal states; control pulse outputting means for detecting a decision error in response to said first internal states and, when detected a decision error, outputting a control pulse; second internal state outputting means for replacing, in response to said received signal and said first internal states, said first internal states with second internal states to control error propagation when said control pulse outputting means has outputted said control pulse and outputting said second internal states, or outputting said first internal states as said second internal states without replacement when said control pulse outputting means does not output said control signal; and estimated value outputting means for updating said second internal states to output said estimated channel impulse response.

Claim 4

A system as claimed in claim 3, wherein said first internal state outputting means comprises: an serial connection of n shift registers to which said result of decision is applied; a first add circuit for weighting signals stored in said n shift registers by a group of n weights fed via input/output terminals and adding resulted weighted signals; a first subtractor for producing an error signal representative of a difference between an output of said first adding circuit and said received signal; and output terminals for outputting said signals of said n shift registers, said n weights, and said error signal as said first internal states.

Claim 5

A system as claimed in claim 4, wherein said control pulse outputting means detects a level of said error signal, compares said level with a predetermined threshold, and, if said level is greater than said threshold, outputs said control pulse.

Claim 6

A system as claimed in claim 4 or 5, wherin said second internal state ouputting means comprises: a control circuit to be enabled by said control pulse; a first switch group having m switches for outputting, in response to m signals of said n shift registers (1 ≦m ≦n ) and outputs of a second switch group having m switches, said m signals of said n shift registers when said control circuit is not enabled or outputting outputs of said second switch group when said control circuit is enabled; an output terminal group having m output terminals for outputting signals from said first switche group; a first switch for outputting, in response to said error signal from said first subtractor and an output of a second switch, said error signal when said control signal is not enabled or outputting said output of said second switch when said control circuit is enabled; a first switch output terminal for ouputting a signal from said first switch; a decision pattern generate circuit enabled by a signal from said control circuit for outputting decision patterns of L (L being a number of levels per symbol) different m symbol sequences; a memory group having n - m memories for storing n - m signals of said n shift registers; an output terminal group having n - m output terminals for outputting said n - m signals; a second add circuit for weighting, by using said n weights of said first add circuit, signals stored in sand n - m memory group and n symbol sequences constituted by said decision patterns constitiuted by said m symbol sequences and adding resulted weighted signals and resulted weighted n symbol sequences; an output terminal group having n output terminals; a second subtractor for producing an error signal representative of a difference between an output of said second add circuit and said received signal; a first power detect circuit for determining and outputting power of an output of said second subtractor; a comparator for comparing outputs of said first and second power detect circuits and, if said output of said first power detect circuit is greater than said output of said second power detect circuit, causing outputs of said m second switch group to be fed to a third switch group having m switches and causing said third switch group to output an output of said second switch while, if said output of said first power detect circuit is smaller than said output of said second power detect circuit, causing said output of said decision pattern generate circuit to be fed to said third switch group and causing said third switch to output an output of said second subtractor; said third switch receiving an output of said second subtractor and an output of said second switch and controlled by said comparator; a memory for storing an output of said third switch; said second power detect circuit detecting power of said signal stored in said memory; said second switch controlled by said control circuit for applying said signal stored in said memory to said first switch when said decision pattern generate circuit has generated all of said patterns or applying said signal to said third switch when said decision pattern generate circuit is generating any of said patterns; said third switch group controlled by said comparator for selectively outputting either one of an output of said decision pattern generate circuit and outputs of said second switch group; a memory group having m memories for storing outputs of said third switch group; and said second switch group controlled by said control circuit for applying said signals stored in said m memory group to said first switch group when said decision pattern generate circuit has generated all of said patterns or applying said signals to said third switch group when said decision pattern generate circuit is generating any one of said patterns.