← Back to Patent Explorer
EP0451999A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Matrix switcher apparatus

Assignee: Sony Corp
•
Filing: 1991-03-28
•
Granted: —
•
Expires: 2011-03-28
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A matrix switcher apparatus provided with a plurality of matrix switcher units each including a plurality of first input terminals, a plurality of second input terminals, a plurality of first output terminals, and a plurality of second output terminals, the plurality of matrix switcher units being arranged in a matrix form, wherein, between the adjacent matrix switcher units, the plurality of first input terminals and the plurality of first output terminals are connected and the plurality of second input terminals and the plurality of second output terminals are connected, thus to constitute a signal switcher of M inputs × N outputs as a whole. Wherein control means for storing identification information to identify the first input terminals and the second output terminals, and for controlling cross points of the matrix switcher units are provided every matrix switcher units, thus to deliver selective instruction signals for signal input and output terminals to the respective control means, whereby the control means control ON/OFF of the cross points on the basis of the selective instruction signals. respectively.

Inventors

  • 👤 Michio Mita.
  • 👤 Junichi Yanagisawa

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-05 18:12
CPC Classifications
H; H04; H04Q; H04Q3/00; H04Q3/42; H04Q3/52; H04Q3/521; H04Q3/523; H04H; H04H60/00; H04H60/02; H04H60/04; H04N; H04N5/00; H04N5/222; H04N5/262; H04N5/268

Claims Analysis

Total Claims: 1
Claim 1
Independent Claim 178 words
A matrix switcher apparatus provided with a plurality of matrix switcher units each including a plurality of first input terminals, a plurality of second input terminals, a plurality of first output terminals, and a plurality of second output terminals, said plurality of matrix switcher units being arranged in a matrix form, wherein, between the adjacent matrix switcher units, said plurality of first input terminals and said plurality of first output terminals are connected and said plurality of second input terminals and said plurality of second output terminals are connected, thus to constitute a signal switcher of M inputs × N outputs as a whole, characterized in that control means for storing identification information to identify said first input terminals and said second output terminals, and for controlling cross points of said matrix switcher units are provided every said matrix switcher units, and that selective instruction signals for signal input and output terminals are delivered to said respective control means, whereby said control means control ON/OFF of said cross points on the basis of said selective instruction signals, respectively.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag