Abstract A signal processor architecture that comprises a data network having multiple ports, a control bus, and a plurality of signal processing clusters connected to at least two ports and the control bus. Each signal processing cluster comprises a system control processor connected to the control bus, a second control bus, and a global bulk memory having multiple ports. A plurality of functional processing elements are connected to the system control processor by way of the second control bus, and each are connected to a port of the global bulk memory. The global bulk memory comprises a subdata flow network having multiple gateways and full crossbar interconnectivity between each of the multiple gateways. The data network and subdata flow network allow data to be transferred between functional processing elements in the signal processing cluster and any functional processing element and global bulk memory in another signal processing cluster, and allow data to be transferred from any functional processing element into and out of the processor architecture. The first control bus is arbitrated for access on a message by message basis and the data network is arbitrated on a message by message basis for transfers between ports. This results in a relatively loose coupling between the signal processing clusters. The second control bus is arbitrated for access on a word by word basis and the global bulk memory is arbitrated for port access on each global bulk memory cycle. This results in tight coupling within each signal processing cluster.
A signal processor architecture which comprises: a data network having multiple ports and full crossbar connectivity between each of said ports for providing communication capability between the multiple ports; a first control bus; and a plurality of signal processing clusters each connected to at least two ports on said data network and each connected to said first control bus.
Claim 2
Dependent Claim
112 words
The signal processor architecture of Claim 1 wherein each signal processing cluster further comprises: a system control processor connected to said first control bus; and a second control bus connected to said system control processor; and a global bulk memory having multiple ports with one of said ports connected to said system control processor by said second control bus and two of said ports connected to two of said ports on said data network; and a plurality of functional processing elements each of which is connected to said system control processor by said second control bus and each of which is connected to one of said ports on said global bulk memory.
Claim 3
Dependent Claim
39 words
The signal processor architecture of claim 2 wherein each signal processing cluster further comprises: at least one first input/output element connected to a port on said data network and to said second control bus and having an input/output interface.
Claim 4
Dependent Claim
101 words
The signal processor architecture of claim 3 wherein: the system control processor arbitrates access to said first control bus on a message by message basis and arbitrates access to said data network on a message by message basis for transfers between ports on said data network resulting in relatively loose coupling between said signal processing clusters; and the system control processor arbitrates access to said second control bus on a word by word basis and arbitrates access to said global bulk memory for port access on each global bulk memory cycle resulting in tight coupling within each said signal processing cluster.
Claim 5
Dependent Claim
132 words
The signal processor architecture of claim 4 wherein said global bulk memory further comprises: means for packing words whose input is connected to each said port; and a global memory bulk is connected to a memory array having a plurality of word-wide columns and wherein said global memory bus has the same plurality of word-wide columns and is connected to the output of each said means for packing words; and means for unpacking words whose input is connected to said global memory bus and whose output is connected to each said port; and means for addressing the memory array wherein for corner turn addressing each of the plurality of word-wide columns is independently addressed; and wherein port access to memory array and global memory bus is arbitrated each memory array cycle time.
Claim 6
Dependent Claim
172 words
The signal processor architecture of claim 5 wherein said data network further comprises: a means for determining priority between ports that attempt to simultaneously access one port via said full crossbar wherein each port has a priority level; and a means for sending busy signals to ports that attempt to access a port currently communicating with another port; and a means for a placing into a pending status a first in time port that attempts to route to a currently busy port until said currently busy port is unbusy wherein said first in time port with pending status receives access to said previously busy port before any second in time port with a higher priority level receives access to said previously busy port; and a means for providing a plurality of message priority levels; and a means for temporarily suspending a low priority message to or from any port on said data network so that a higher priority message can be sent to or from that same port on said data network.
Claim 7
Dependent Claim
97 words
The signal processor architecture of claim 6 wherein said global bulk memory further comprises: a sub data flow network having multiple gateways and full crossbar interconnectivity between each of said multiple gateways; and wherein each of said multiple ports on said global bulk memory are connected to one of said multiple gateways on said sub data flow network so that data can be transferred via said sub data flow network between any of said functional processing elements and between any functional processing element and said data network ports connected to said ports on said global bulk memory.
Claim 8
Dependent Claim
94 words
The signal processor architecture of claim 7 wherein said subdata flow network together with said data flow network provide: a means whereby data can be transferred via said subdata flow network and said data network between any of said functional processing elements in one said signal processing cluster and any said functional processing elements and said global bulk memory in another said signal processing cluster; and a means whereby data can be transferred via said subdata flow network and said data network between any of said functional processing elements and said first input/output elements.
Claim 9
Dependent Claim
75 words
The signal processor architecture of claim 8 that further comprises: a first test and maintenance bus connected to said data network and to each said system control processor in each said cluster; and a plurality of second test and maintenance buses wherein one said second test and maintenance bus is connected within each said signal processing cluster to said system control processor, said global bulk memory, each said functional processing element and said input/output element.
Claim 10
Dependent Claim
29 words
The signal processor architecture of claim 9 that further comprises: at least one second input/output element connected to said first control bus and said first test and maintenance bus.
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