EP0450863A2
Expired / Lapsed
EP
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Integrated circuit for analog system
Assignee: Pilkington Micro Electronics Ltd
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Filing: 1991-03-27
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Granted: —
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Expires: 2011-03-27
Abstract
Abstract This invention relates to semiconductor integrated circuits which find utility in analogue systems. An integrated circuit of the invention comprises an array (A) of configurable analogue cells (CL) each of which is capable of interconnection with other cells in the array by means of an interconnection network (HB, VB). Each of the cells can be selectively and individually selected by means of select signals (SS) and (DD) emanating from shift registers (DSRH, PSRV). When selected the cell (CL) may be configured with configuration data (DD, AD) which both sets the cell to take up a particular electrical configuration by means of digital data (DD) and sets various programmable resistors and capacitors (P/res, P/cap) in the cells to particular values by means of analogue signals (AD). The configuration data is held in a random access memory RAM. Some of this data is converted to analogue form (AD) by means of a ditigal-to-analogue converter (DAC). The circuit is controlled by a central control (CC) and is capable of being configured to implement particular analogue functional applications from a plurality of possible analogue functional applications. Provision in the circuitry is made to automatically compensate for manufacturing component tolerances.
Inventors
- 👤 Kenneth Austin
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 17:30
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/02; G11C27/024; G11C27/026; G11C17/00; G11C17/14; G11C17/18; G11C5/00; G11C5/02; G11C5/025; G11C7/00; G11C7/06
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
88 words
A semiconductor integrated circuit comprising an arrangement of a plurality of configurable analogue cells (CL) each cell being capable of interconnection with other cells of the arrangement by means of an interconnection network, characterised in that each analogue cell (CL) is capable of being selectively and individually accessed with cell configuration data (AD,DD) to internally configure the cell and effect interconnection of the accessed analogue cell with other analogue cells of the arrangement to implement a particular analogue functional application from a plurality of possible analogue functional applications.
Claim 2
Dependent Claim
94 words
A semiconductor integrated circuit as claimed in claim 1, characterised in that the arrangement further comprises first data paths (DD) incorporating switch control paths (D,D) and the interconnection network includes associated switch circuits (IS1, IS2, IS3, IS0), wherein cell configuration data stored in storage means (RAM) in digital form is directed to an individually accessed selected cell (CL) in digital form over a switch control path (D,D) to effect operation of the associated switch circuits (IS1, IS2, IS3, IS0) and interconnection of the selected analogue cell (CL) with other analogue cells of the arrangement.
Claim 3
Dependent Claim
38 words
A semiconductor integrated circuit as claimed in claim 2, wherein the switch circuits (IS1, IS2, IS3, IS0) each include a switch storage means (SRAM) to store configuration data and a transistor switch (TR) serving as an interconnecting device
Claim 4
Dependent Claim
77 words
A semiconductor integrated circuit as claimed in claim 2 or claim M, wherein the interconnection network comprises a global interconnect system (HB, VB) and a local interconnect system wherein the global interconnect system (HB, VB) is employed to interconnect any cell to any other cell which is located at a distance within the arrangement and the local interconnect system is employed to interconnect the output (OP) of each cell to the inputs (IP1, IP2) of neighbouring cells.
Claim 5
Dependent Claim
71 words
A semiconductor integrated circuit as claimed in any one preceding claim, wherein an analogue cell (CL) comprises, an amplifier (OA), programmable analogue components (P/res. P/cap), switching means (PT) and signal paths (IIP, NIIP, OP), and wherein to implement any predetermined analogue circuit, the analogue components are programmed for required intrinsic values and the switching means (PT) are utilised to interconnect the programmed components and signal paths in a particular predetermined configuration.
Claim 6
Dependent Claim
22 words
A semiconductor integrated circuit as claimed in claim 5, wherein intrinsic component values are stored in digital form in the storage means.
Claim 7
Dependent Claim
66 words
A semiconductor integrated circuit as claimed in claim 5 or claim 6, wherein the arrangement includes selection signal paths (SS, DD) adapted for selecting individual analogue cells wherein cell selection signals (SEL, EN) emanate from signal generating means (PSRH, PSRV) under the control of a central control means (CC) and are successively directed to the selection signal paths (SS, DD) associated with individual analogue cells (CL).
Claim 8
Dependent Claim
63 words
A semiconductor integrated circuit as claimed in claim 5, claim 6 or claim 7, wherein the arrangement includes second data paths (AD) for providing analogue data to each analogue cell (CL) the analogue data having been converted from digital cell configuration data by ditigal-to-analogue conversion means (DAC), wherein the analogue data is directed over the second data paths (AD) to the selected cell.
Claim 9
Dependent Claim
40 words
A semiconductor integrated circuit as claimed in claim 8 wherein the analogue data comprises a plurality of separate analogue signals (AD) each of which represents a particular value of a component which is to be programmed in the analogue cell.
Claim 10
Dependent Claim
38 words
A semiconductor integrated circuit as claimed in any one preceding claim, wherein the arrangement of the plurality of configurable analogue cells (CL) takes the form of an array (A) where the cells are arranged in rows and columns.
Claim 11
Dependent Claim
80 words
A semiconductor integrated circuit as claimed in claim 10, wherein the signal generating means (PSRH, PSRV) comprises a first programming shift register and a second programming shift register wherein the first programming shift register provides horizontal coordinate reference signals (SS) within the array, (A), whereas the second programming shift register provides vertical coordinate reference signals (SEL,EN) within the array (A), the horizontal (S) and vertical (SEL,EN) coordinate reference signals enabling selection of any analogue cell (CL) within the array (A).
Claim 12
Dependent Claim
42 words
A semiconductor integrated circuit as claimed in claim 11, wherein the global interconnect system includes horizontal global bus lines (HB) running horizontally between the rows of analogue cells and vertical global bus lines (VB) running vertically between the columns of analogue cells.
Claim 13
Dependent Claim
42 words
A semiconductor integrated circuit as claimed in claim 12, wherein at all edges of the array there are provided switch blocks (ES) which enable the vertical and horizontal global bus (VB,HB) lines at the edges of the array to be directly interconnected.
Claim 14
Dependent Claim
77 words
A semiconductor integrated circuit as claimed in any one claim from claim 10 to claim 13, wherein the semiconductor integrated circuit is adapted to produce a programmable resistor component (P/res) which comprises a pair of matched characteristic field effect transistors (M3, M4-M12, M13) having gate, source and drain electrodes, wherein the first transistor (M4-M13) of the pair serves as a reference transistor and the second transistor (M3-M12) of the pair serves to provide the actual resistor value.
Claim 15
Dependent Claim
163 words
A semiconductor integrated circuit as claimed in claim 14, wherein the semiconductor circuit further comprises, a differential amplifier (N/CC, P/CC), an adjustable constant current source (CCS), and first (1.5V) and second (2.5V) reference potentials, and wherein the constant current source (CCS) serves as a load for the reference transistor (M4-M13) said reference transistor (M4-M13) being connected to provide a negative feedback path to the differential amplifier (N/CC, P/CC) whereby the operation of the differential amplifier (N/CC, P/CC) is arranged to adjust the gate electrode voltage of said reference transistor (M4-M13) until a specific voltage drop (IV) relative to the first and second reference potentials (1.5V 2.5v) appears across said reference transistor (M4-M13) to thereby establish a predetermined resistance between the source and drain electrodes of said reference transistor and whereby the gate electrode voltage of said reference transistor is arranged to directly control the conductance of the second transistor of said matched characteristic field effect transistors (M3,M4-M12,M13) to set the required resistor value.
Claim 16
Dependent Claim
71 words
A semiconductor integrated circuit as claimed in claim 15, wherein the semiconductor integrated circuit is adapted to produce a linear resistor by the provision of a complementary pair of matched characteristic field effect transistors (M4,M3-M13,M12) of opposite polarity types whereby the second transistors of each matched characteristic field effect transistors (M13,M12) are connected in parallel and whereby in operation of said second transistors (M13,M12) a linear transfer characteristic function is achieved.
Claim 17
Dependent Claim
87 words
A semiconductor integrated circuit as claimed in claim 16, wherein each programmable resistor comprises a resistor network (R/BLK) including a plurality of pairs (N/RE1, P/RE1 ...... N/RE6, P/RE6) of opposite polarity field effect transistors being arranged to be capable of producing different ranges of resistor values, wherein a particular range is selected by cell configuration data extending over a data bus (DBB) incorporated in said first data paths (DD) to a memory means (RAMB) whose output is adapted to switch the selected range of resistors into operation.
Claim 18
Dependent Claim
29 words
A semiconductor integrated circuit as claimed in claim 15, claim 16 or claim 17, wherein the adjustable constant current source is adjusted by means of the analogue signals (AD).
Claim 19
Dependent Claim
29 words
A semiconductor integrated circuit as claimed in any one preceding claim, wherein the integrated circuit includes programmable capacitor components (P/cap) which include at least one capacitor multiplier circuit (M1,M2).
Claim 20
Dependent Claim
47 words
A semiconductor integrated circuit as claimed in claim 19, wherein each opposite polarity field effect transistor has an associated capacitive analogue storage circuit (N/STR,P/STR) capable of storing and retaining an analogue potential on the gate electrode of said reference transistor when said specific voltage drop is attained.
Claim 21
Dependent Claim
34 words
A semiconductor integrated circuit as claimed in any preceding claim, wherein manufacturing component tolerances for all analogue components are automatically compensated for by a single external resistor (ERR1) and a single external capacitor (ERC1).
References Cited (Backward Citations)
No citation records indexed.
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