← Back to Patent Explorer
EP0450839A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

A logic simulation machine

Assignee: International Business Machines Corp
•
Filing: 1991-03-26
•
Granted: —
•
Expires: 2011-03-26
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A logic simulation machine includes a trace gatherer which generates an all events trace (AET) which is a record of what has happened to all or a subset of the facilities by monitoring a simulation bus on which the logic simulation machine put a calculated result during the simulation thereon. The AET gatherer allows an AET to be gathered without slowing the simulation. The AET gatherer is an auxiliary processor that is connected to the simulation bus in the logic simulation machine in parallel with simulation processors of the machine.

Inventors

  • 👤 Gerald Bernard Long
  • 👤 Mark David Sweet

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-08 06:13
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G06F11/30; G06F11/34; G06F11/3457; G06F11/3466; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F11/348; G06F11/349

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 84 words
A logic simulation machine comprising a simulation processor operable to simulate digital logic characterised by a trace gatherer comprising a current state store means for storing current states of a model being simulated, a change record store for storing changes in the current states of the model, and a control means for monitoring the current states of the model being simulated to detect a change in the current states stored in the current state store and store the change into the change record store.
Claim 2
Dependent Claim 45 words
A machine as claimed in Claim 1, having a plurality of simulation processors connected in parallel by a simulation bus, said trace gatherer being connected to said simulation bus and each simulation processor say arranged to place simulated results on the simulation bus in parallel.
Claim 3
Dependent Claim 32 words
A machine as claimed in Claim 1 or Claim 2 in which said trace gatherer includes a vast memory adapted to store a mask defining nodes to be traced during a simulation.
Claim 4
Independent Claim 75 words
A method of operating a logic simulation machine including a current state store means and a change record means, comprising the steps of: storing current states of a model being simulated by the logic simulation machine in the current state store means; monitoring the current states of the model being simulated to detect a change in the current states stored in the current state store means; and storing the change into the change record means.
Claim 5
Dependent Claim 48 words
A method as claimed in Claim 4 wherein the logic simulation machine further includes a plurality of simulation processors and a simulation bus means on which each simulation processor puts a simulated current state, further including the step of: receiving the simulated state from the simulation bus means.
Claim 6
Dependent Claim 56 words
A method as claimed in Claim 4 wherein the logic simulation machine further includes a memory means equal in size to the current state store means, further including the step of: storing, in the memory means, a mask means for indicating which node to be traced to trace a subset of all facilities during a simulation.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag