Parallel pipelined instruction processing system for very long instruction word

Abstract

Abstract A parallel pipelined instruction processing system for executing a plurality of instructions in parallel without no branch delay, comprises a instruction block fetch unit for fetching an instruction block including at least one instruction field and one branch instruction field, at least one instruction execution unit receiving an instruction included in the instruction field of the instruction block held in the instruction block fetch unit and for executing the received instruction, and a branch instruction execution unit receiving a branch instruction included in the branch instruction field of the instruction block held in the instruction block fetch unit and for executing a processing for the received branch instruction. The branch instruction execution unit includes an operand fetch circuit receiving the branch instruction included in the branch instruction field of the fetched instruction block for fetching, from a data register group, an operand to be used for the received branch instruction, and an address generation circuit receiving the branch instruction included in the branch instruction field of the fetched instruction block and for simultaneously generating a next address of an instruction to be next fetched and a branch destination address for the received branch instruction. The address generation circuit operates to output one of the next address and the branch destination address on the basis of the content of the operand fetch circuit.

Inventors

• 👤 Isako C/O Nec Corporation Ishikawa
• 👤 Yumiko C/O Nec Corporation Ushimaru

Bibliographic Details