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EP0450320A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Semiconductor integrated circuit device for high frequency signal processing

Assignee: Toshiba Corp
•
Filing: 1991-03-04
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Granted: —
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Expires: 2011-03-04
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Abstract

Abstract A semiconductor integrated circuit device comprises a multilevel interconnection structure which includes upper interconnection layers (44, 43) provided on an interlevel insulator (42). A part of at least one of upper interconnection layers (44) disposed on the interlevel insulator (42) is used as an electrode pad (44) to reduce an unwanted stray capacitance between the electrode pad (44) and a semiconductor substrate (30).

Inventors

  • 👤 Shuji C/O Int. Property Division Watanabe
  • 👤 Hideki C/O Int. Property Division Takada

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-09 16:53
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; H10D; H10D84/00; H10D89/00; H10D89/60; H10D89/601; H10W20/00; H10W20/40; H10W20/495; H10W20/496; H10W72/981; H10W72/983

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 95 words
A semiconductor integrated circuit device comprising a plurality of circuit elements provide in a semiconductor substrate (30), isolation regions (33) for electrically isolating said circuit elements from one another, a multilevel interconnection structure having upper and lower interconnection layers (43, 44) (36, 37, 38) and an interlevel insulator (42) provided between said upper and lower interconnection layers, and electrode pads (44) provided above said semiconductor substrate, characterized in that a part of at least of said upper interconnection layers (44) provided on said interlevel insulator (42) is used as each of said electrode pads (44).
Claim 2
Dependent Claim 26 words
The semiconductor integrated circuit device according to claim 1, characterized in that said electrode pads (44) are provided above a periphery of said semiconductor substrate (30).
Claim 3
Dependent Claim 34 words
The semiconductor integrated circuit device according to claim 2, characterized in that each of said electrode pads (44) is provided at an end portion of at least one of said upper interconnection layers (44).
Claim 4
Dependent Claim 27 words
The semiconductor integrated circuit device according to claim 1, characterized in that each of said electrode pads (44) is provided on each of said interlevel insulator (42).
Claim 5
Dependent Claim 18 words
The semiconductor integrated circuit device according to claim 1, characterized in that said electrode pads (44) are square.
Claim 6
Dependent Claim 31 words
The semiconductor integrated circuit device according to claim 1, characterized in that said upper interconnection layers (43, 44) are covered with a surface passivation layer (39) except said electrode pads (44).
Claim 7
Dependent Claim 32 words
The semiconductor integrated circuit device according to claim 1, characterized in that said lower interconnection layers (36, 37, 38) are provided on an insulating film (35) formed on said semiconductor substrate (30).
Claim 8
Dependent Claim 51 words
The semiconductor integrated circuit device according to claim 1, characterized in that a total thickness of an insulating film located between each of said electrode pads (44) and said semiconductor substrate (30) is the sum of a thickness of said interlevel insulator (42) and a thickness of said insulating film (35).
Claim 9
Dependent Claim 32 words
The semiconductor integrated circuit device according to claim 1, characterized in that each of said circuit elements is comprised of a bipolar transistor having emitter, base and collector regions (E, B, C).
Claim 10
Dependent Claim 32 words
The semiconductor integrated circuit device according to claim 9, characterized in that said emitter, base and collector regions (E, B, C) are electrically connected to said lower interconnection layer (36, 37, 38).
Claim 11
Dependent Claim 27 words
The semiconductor integrated circuit device according to claim 9, characterized in that said collector region (C) is electrically connected to one of said upper interconnection layers (44).
Claim 12
Dependent Claim 23 words
The semiconductor integrated circuit device according to claim 7, characterized in that said interlevel insulator (42) is thicker than said insulating film (35).

References Cited (Backward Citations)

EP0019883A2 Cited
DE3116406A1 Cited
EP0260906A2 Cited

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