EP0449610A2
Expired / Lapsed
EP
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Electrically erasable programmable read-only memory with threshold value measurement circuit
Assignee: Toshiba Corp
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Filing: 1991-03-27
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Granted: —
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Expires: 2011-03-27
Abstract
Abstract A NAND cell type electrically erasable programmable read-only memory (10) has NAND cell units (MB1, MB2,..., MBn). Each NAND cell unit has a series array of floating gate type metal-oxide semiconductor field effect transistors (Mi1, Mi2,..., Mi8) as memory cell transistors. The first-stage memory cell transistor (Mi1) is connected at its gate to a corresponding bit line (BLi) via a first select transistor (Qi1). The last-stage memory cell transistor (Mi8) is connected at its source to a common source line (60) by means of a second select transistor (Qi2). The common source line (60) is connected with a test circuit (62) to be used for measuring the distribution of threshold values of the memory cell transistors (M) in the erasing state. The test circuit (62) temporarily applies the common source line (60) with a positive bias voltage (Vbias) of a predetermined potential level so that the potential (Vcgj) of the control gate of a selected memory cell transistor (Mij) is set at 0 volt. As a result, the threshold value of the EEPROM (10) in the erasing state can be measured without using any negative potential.
Inventors
- 👤 Yoshiyuki C/O Intellectual Property Div. Tanaka
- 👤 Masaki C/O Intellectual Property Div. Momodomi
- 👤 Fujio C/O Intellectual Property Div. Masuoka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 20:16
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/50; G11C29/50004; G11C16/00; G11C16/02; G11C16/04; G11C16/0483; G11C16/06; G11C16/10; G11C16/14; G11C16/34; G06; G06F; G06F2201/00; G06F2201/81
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
215 words
An electrically erasable nonvolatile semiconductor memory device comprising a semiconductive substrate (12, 92), parallel data transfer lines (BL) arranged on said substrate (12, 92), parallel control gate lines (WL) provided on said substrate to insulatively intersect said data transfer lines so as to define intersections therebetween, and metal insulator semiconductor field effect transistors arranged at said intersections as memory cell transistors, wherein each memory cell transistor has a control gate electrode and a charge storage portion, and is connected at the control gate electrode thereof to a corresponding one of said control gate lines (WL), and wherein said memory cell transistors (M) defining a plurality of cell units each of which has a preselected number of series-connected memory cell transistors (MiL to Mi8) having a first end connected to a corresponding one of said data transfer lines (BL) and a second end connected to a source line (60) together with the other series-connected memory cell transistors, characterized in that a bias means (62, 102) is provided for being operative, when specified, to raise the voltage on said source line (60) by a previously selected bias potential (Vbias), thereby to permit the measurement of distribution of the threshold voltages of said memory cell transistors (M) in an erasing state while inhibiting use of a negative voltage.
Claim 2
Dependent Claim
88 words
The device as recited in claim 1, characterized in that said bias means (62, 102) applies substantially zero volt to a selected one of said control gate lines (WL), and applies the remaining control gate line or lines with a readout voltage to be used in a data readout mode of said device, whereby the potential of the control gate electrodes of an array of memory cell transistors (M) connected together to the selected control gate line is lower than the voltage on said common source line (60).
Claim 3
Dependent Claim
54 words
The device as recited in claim 2, characterized in that said bias means (62, 102) has a switching transistor (T2) which is connected to said common source line (60), and receives a positive voltage (Vbias) externally supplied thereto, and is rendered conductive to apply the positive voltage (Vbias) to said common source line (60).
Claim 4
Dependent Claim
50 words
The device as recited in claim 3, characterized in that said substrate (92) has in its surface area thereof a first semiconductor well region (94) which is different from said substrate in the conductivity type, and in that said memory cell transistors (M) are arranged in said first well region.
Claim 5
Dependent Claim
54 words
The device as recited in claim 4, characterized in that said substrate (92) has in another surface area thereof a second semiconductor well region (98) which is different from said substrate in the conductivity type and electrically isolated from said first well region, said bias means being arranged in said second well region (98).
Claim 6
Dependent Claim
24 words
The device as recited in claim 5, characterized in that said common source line (60) is electrically connected to said first well region (94).
Claim 7
Dependent Claim
208 words
An electrically erasable programmable read-only memory comprising a semiconductive substrate (12), bit lines (BL) insulatively arranged on said substrate, word lines (WL) arranged to insulatively intersect said bit lines on said substrate, memory cell sections (MB) each of which has as memory cell transistors a preselected number of arrayed floating gate type field effect transistors connected to said bit lines and said word lines, a first switching transistor (Qi1) provided at a first end of each memory cell section (MBi) to selectively connect it to a corresponding bit line (BLi), and a second switching transistor (Qi2) provided at a second end of each memory cell section (MBi) to selectively connect it to a source potential line (60), characterized in that said memory further comprises voltage adjusting means (62, 102) associated with said word lines (WL) and said source potential line (60), for selectively applying a positive DC voltage (Vbias) having a predetermined potential level to said common source potential line (60) in response to an externally supplied electrical signal (TEST, TEST ), and for maintaining the potential on a word line (WLi) associated with a memory cell transistor (Mij) which is selected from said memory cell transistors (M) at a level lower than said positive DC voltage (Vbias).
Claim 8
Dependent Claim
75 words
The memory as recited in claim 7, characterized in that said voltage adjusting means (62, 102) comprises a logic gate circuit (64) for externally receiving said electrical signal, and a transistor circuit (T1 to T4) which is connected to said logic gate circuit (64) and externally receives said positive DC voltage (Vbias) to selectively vary the potential of said source line (60) within a range between said positive DC voltage (Vbias) and the ground potential.
Claim 9
Dependent Claim
24 words
The memory as recited in claim 8, characterized in that said transistor circuit (T1 to T4) includes a metal insulator semiconductor field effect transistor.
Claim 10
Independent Claim
151 words
A method of measuring threshold voltages of memory cell transistors suitable for an electrically erasable programmable read-only memory which comprises bit lines (BL) insulatively arranged on a semiconductive substrate (12), word lines (WL) provided to insulatively intersect said bit lines on said substrate, and memory cell sections (MB) each of which has as memory cell transistors a preselected number of arrayed floating gate type field effect transistors connected to said bit lines and said word lines, characterized in that said method comprises the steps of temporarily setting the potential on a common source potential line (60) to which said memory cell sections (MB) are connected to a positive DC voltage (Vbias) having a predetermined potential level, and substantially simultaneously, maintaining the potential on a word line (WLi) associated with a memory cell transistor (Mij) selected from said memory cell transistors (M) at a level lower than said positive DC voltage (Vbias).
Claim 11
Dependent Claim
44 words
The method as recited in claim 10, characterized by further comprising the step of maintaining potentials on word lines (WL) associated with the remaining memory cell transistors (M) at a specified potential to be used in the ordinary data readout mode of said memory.
Claim 12
Dependent Claim
52 words
The method as recited in claim 11, characterized in that a surface area (96) of said substrate (92) in which said memory section (MB) is arranged is electrically isolated from another surface area of said substrate (92) while said positive DC voltage (Vbias) is being applied to said common source line (60).
References Cited (Backward Citations)
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