On-chip voltage regulator and semiconductor memory device using the same

Claim 2

An on-chip voltage regulator as claimed in claim 1, characterized in that said regulator means comprises means (I, Q26 - Q30) for outputting a first gate voltage (VI) supplied to the gate of said regulator transistor when said predetermined clock signal is maintained at a first state and for generating a second gate voltage (V1 + V2) supplied to the gate of said regulator transistor when said predetermined clock signal is maintained at a second state.

Claim 3

An on-chip voltage regulator as claimed in claim 1, characterized in that said voltage regulator comprises means (I, Q26 - Q30) for increasing said gate voltage output to the gate of said regulator transistor when said predetermined clock signal changes from a first state indicating that said internal circuit is maintained in a standby mode to a second state indicating said internal circuit is operating.

Claim 4

An on-chip voltage regulator as claimed in claim 1, characterized in that said on-chip voltage regulator further comprises pulse generating means (60) for generating said predetermined clock signal from a state indicating signal indicating whether or not said internal circuit is operating.

Claim 5

An on-chip voltage regulator as claimed in claim 4, characterized in that said pulse generating means generates a one-shot pulse ( CLX1 ) when said state indicating signal indicates that said internal circuit starts to operate.

Claim 6

An on-chip voltage regulator as claimed in claim 1, characterized in that said on-chip voltage regulator comprises pulse generating means (Q30, Q31) for receiving a plurality of state indicating signals ( RAS , CAS ) which indicate whether or not respective corresponding parts of said internal circuit are operating and for generating said predetermined clock signal from said plurality of state indicating signals.

Claim 7

An on-chip voltage regulator as claimed in claim 1, characterized in that said regulator means comprises: a constant-current source (I) connectable to receive a first predetermined power supply voltage (V A , V EXT ); first voltage generating means (Q26 - Q28), connected to said constant-current source in series and connected to the gate of said regulator transistor, for generating a first voltage (V1) from a constant current generated by said constant-current source; second voltage generating means (Q29), connected to said first voltage generating means in series and connectable to receive a second predetermined power supply voltage (ground level) lower than said first predetermined voltage, for generating a second voltage (V2) from said constant current supplied from said constant-current source through said first voltage generating means; and control means (Q30), coupled to said second voltage generating means, for selectively short-circuiting said second voltage generating means on the basis of the state of said predetermined clock signal so that either a voltage equal to the sum (V1 + V2) of said first voltage and second voltage or said first voltage (V1) is selectively output, as said gate voltage, to the gate of said regulator transistor.

Claim 8

An on-chip voltage regulator as claimed in claim 7, characterized in that: said first voltage generating means comprises m field effect transistors (Q26 - Q28) where m is an integer equal to or larger than 1; said m field effect transistors are diode-connected and connected in series; and said first voltage substantially corresponds to the sum of threshold voltages of said m field effect transistors.

Claim 9

An on-chip voltage regulator as claimed in claim 7, characterized in that: said second voltage generating means comprises n field effect transistors (Q29) where n is an integer equal to or larger than 1; said n field effect transistors are diode-connected and connected in series; and said second voltage substantially corresponds to the sum of threshold voltages of said n field effect transistors.

Claim 10

An on-chip voltage regulator as claimed in claim 7, characterized in that said control means comprises a transistor (Q30) having a control terminal connectable to receive said predetermined clock signal ( CLK , CLK1 ), a first terminal connected to a node where said first voltage generating means and said second voltage generating means are connected in series, and a second terminal connectable to receive said second predetermined power supply voltage.

Claim 11

An on-chip voltage regulator as claimed in claim 7, characterized in that: said constant-current source comprises a field effect transistor (Q25) of a depletion type; and said field effect transistor of said constant-current source comprises a gate terminal, a first terminal connectable to receive said first predetermined power supply voltage, and a second terminal connected to said gate terminal and the gate of said regulator transistor.

Claim 12

An on-chip voltage regulator as claimed in claim 11, characterized in that said field effect transistor comprises: a substrate (1) having a first conductivity type; a first well (2) formed in said substrate and having a second conductivity type opposite to said first conductivity type; a second well (3) formed in said first well and having the first conductivity type; a first diffusion region (S) formed in said second well and having the second conductivity type, said first diffusion region corresponding to said first terminal; a second diffusion region (D) formed in said second well and having the second conductivity type, said second diffusion region corresponding to said second terminal; and a gate (G) positioned between said first and second diffusion regions, said gate corresponding to said gate terminal.

Claim 13

An on-chip voltage regulator as claimed in claim 12, characterized in that said first well is connectable to receive said external power supply voltage (V EXT ).

Claim 14

An on-chip voltage regulator as claimed in claim 11, characterized in that said first predetermined power supply voltage is equal to said external power supply voltage.

Claim 15

An on-chip voltage regulator as claimed in claim 11, characterized in that said field effect transistor comprises: a substrate (4) having a first conductivity type; a well (5) formed in said substrate and having a second conductivity type opposite to said first conductivity type; a first diffusion region (S) formed in said well and having the first conductivity type, said first diffusion region corresponding to said first terminal; a second diffusion region (D) formed in said well and having the first conductivity type, said second diffusion region corresponding to said second terminal; and a gate (G) positioned between said first and second diffusion regions, said gate corresponding to said gate terminal.

Claim 16

An on-chip voltage regulator as claimed in claim 15, characterized in that said first well is connectable to receive said external power supply voltage.

Claim 17

An on-chip voltage regulator as claimed in claim 7, characterized in that said on-chip voltage regulator comprises a capacitor having a first terminal coupled to the gate of said regulator transistor, and a second terminal connectable to receive said reference voltage.

Claim 18

An on-chip voltage regulator as claimed in claim 1, characterized in that said regulator means comprises means (Q26 - Q30) for changing an internal resistance of said regulator transistor on the basis of the state of said predetermined clock.

Claim 19

An on-chip voltage regulator as claimed in claim 1, characterized in that said regulator means comprises: constant-current generation means (I) for generating a constant current; and variable resistance means (Q29 - Q30), coupled to said constant-current generation means and said regulator transistor, for providing a variable resistance dependent on the state of said predetermined clock and for outputting a voltage (V1. V1 + V2) obtained by passing said constant current through said variable resistance means to the gate of said regulator transistor.

Claim 20

A semiconductor memory device comprising: a first system (300) operating in accordance with a first clock signal (φ s , φ s ) and having a memory cell array (10) and a sense amplifier (24) coupled to said memory cell array; a second system (200) operating in accordance with a second clock signal ( RAS ) and having row address means (12a, 12b, 16) for generating a row address from an external address and for outputting said row address to said memory cell array; and a third system operating in accordance with a third clock signal (ATD, CAS ) and having column address means (12a, 12b, 14) for generating a column address from said external address and for outputting said column address to said memory cell array, characterized in that said semiconductor memory device comprises internal voltage generating means (500), coupled to said first, second and third systems, for generating first, second and third internal voltages (V INT1 , V INT2 , V INT3 ) from an external power supply voltage (V EXT ) on the basis of states of said first, second and third clock signals and for outputting said first, second and third internal voltages to said first, second and third systems, respectively, and characterized in that said internal voltage generating means comprises: a regulator transistor (Q1) provided for each of said first, second and third systems and having a first terminal connectable to receive said external power supply voltage and a second terminal connected to a corresponding one of said first, second and third systems; and regulator means, connected to said regulator transistor, for generating a gate voltage (V G1 ) output to the gate of said regulator transistor on the basis of the state of at least one of said first, second and third clock signals so that a corresponding one of said first, second and third internal voltages is substantially fixed irrespective of whether or not said corresponding one of the first, second and third systems is operating.

Claim 21

A semiconductor memory device as claimed in claim 20, characterized in that: said regulator means comprises means (39) for controlling the gate voltage output to the gate of said regulator transistor provided for said first system on the basis of the state of said first clock signal; and said first clock signal is synchronized with a sense amplifier driving signal (φ s , φ s ) which drives said sense amplifier.

Claim 22

A semiconductor memory device as claimed in claim 21, characterized by further comprising pulse generating means (60) for generating a one-shot pulse ( CLX1 ) from said sense amplifier driving signal, said one-shot pulse corresponding to said first clock signal.

Claim 23

A semiconductor memory device as claimed in claim 20, characterized in that: said regulator means comprises means (38) for generating the gate voltage output to the gate of said regulator transistor provided for said second system on the basis of the state of said second clock signal; and said second clock signal is a row address strobe signal supplied from an external device.

Claim 24

A semiconductor memory device as claimed in claim 20, characterized in that: said regulator means comprises means (39) for generating the gate voltage output to the gate of said regulator transistor provided for said second system on the basis of the state of said second clock signal; and said semiconductor memory device comprises address transition detection means (27₀ - 27₁₀, T₀ - T₁₀, R1, INV, PWC) for detecting a change in said external address and for outputting a pulse signal (ATD) when the change in said external address is detected, said pulse signal corresponding to said second clock signal.

Claim 25

A semiconductor memory device as claimed in claim 20, characterized in that said regulator means comprises means (Q26 - Q31) for generating the gate voltage output to the gate of said regulator transistor provided for each of said second and third systems on the basis of the states of said second and third clock signals ( RAS , CAS ).

Claim 26

A semiconductor integrated circuit device comprising: a regulator transistor (Q1) having a first terminal connectable to receive an external power supply voltage (V EXT ), a second terminal through which an internal power supply voltage (V INT ) lower than said external power supply voltage, and a gate, characterized in that said semiconductor integrated circuit device comprises means (100, 100A), coupled to the gate of said regulator transistor, for changing an internal resistance of said regulator transistor in accordance with a clock which controls active/inactive states of an internal circuit of said semiconductor integrated circuit device to thereby suppress a difference between the internal power supply voltage obtained when the internal circuit is maintained in the active state and the internal power supply voltage obtained when the internal circuit is maintained in the inactive state.

Claim 27

A semiconductor integrated circuit device comprising: an on-chip voltage control circuit (Q1) which drops an external power supply voltage (V EXT ) to thereby generate an internal power supply voltage (V INT ) supplied to an internal circuit of said semiconductor integrated circuit device, characterized in that said semiconductor integrated circuit device comprises means (100, 100A), coupled to said on-chip voltage control circuit, for controlling a current supply ability of said on-chip voltage control circuit so that said current supply ability obtained when said internal circuit is maintained in an active state is greater than said current supply ability obtained when said internal circuit is maintained in an inactive state.

Claim 28

A semiconductor integrated circuit device comprising: an on-chip voltage control circuit (Q1) which drops an external power supply voltage (V EXT ) to thereby generate an internal power supply voltage (V INT ) supplied to an internal circuit of said semiconductor integrated circuit device, characterized in that said semiconductor integrated circuit device comprises means (100, 100A), coupled to said on-chip voltage control circuit, for controlling a current supply ability of said on-chip voltage control circuit so that said current supply ability increases temporarily in response to a switching of a state of said internal circuit from an inactive state to an active state.

Claim 29

A semiconductor integrated circuit device comprising: a first system (400) operating in accordance with a sense amplifier driving signal and having a memory cell array and a sense amplifier coupled to said memory cell array; a second system (200) operating in accordance with a row address strobe signal and having row address means for generating a row address from an external address and for outputting said row address to said memory cell array; and a third system (300) operating in accordance with a column address strobe signal signal and having column address means for generating a column address from said external address and for outputting said column address to said memory cell array, characterized in that said semiconductor integrated circuit device comprises: an on-chip voltage control circuit (Q1, 100, 100A) which is coupled to said first, second and third systems which generates first, second and third internal power supply voltages from an external power supply voltage, said on-chip voltage control circuit comprising means (100, 100A) for controlling a current driving ability of said on-chip voltage control circuit in accordance with at least one predetermined clock signal.

Claim 30

A semiconductor integrated circuit device as claimed in claim 29, characterized in that said on-chip voltage control circuit comprises: first internal power supply voltage generating means (39) for inputting a first predetermined clock signal which is the same as or synchronized with said sense amplifier driving signal and for generating a first internal power supply voltage (V INT3 ) to said first system; second internal power supply voltage generating means (37) for inputting a second predetermined clock signal which is the same as or synchronized with said row address strobe signal and for generating a second internal power supply voltage (V INT1 ) to said second system; and third internal power supply voltage generating means (38) for inputting a third predetermined clock signal which is the same as or synchronized with said column address strobe signal and for generating a third internal power supply voltage (V INT2 ) to said third system.