EP0448374A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method for fabricating a semiconductor device having a capacitor with polycrystalline silicon having micro roughness on the surface
Assignee: NEC Corp
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Filing: 1991-03-20
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Granted: —
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Expires: 2011-03-20
Abstract
Abstract A method for fabricating a polycrystalline silicon having a roughed surface, which is useful for a capacitor electrode is disclosed. The method is featured by depositing a polycrystalline silicon layer in such a manner that grains of silicon are caused at the surface of the polycrystalline silicon layer. The polycrystalline silicon layer thus obtained has a large effective surface area and is suitable for a capacitor electrode because of its increased effective surface area.
Inventors
- 👤 Hirohito C/O Nec Corporation Watanabe
- 👤 Toru C/O Nec Corporation Tatsumi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 07:28
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/712; H10D1/716; Y; Y10; Y10S; Y10S438/00; Y10S438/964
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
61 words
A method of fabricating a semiconductor device comprising the steps of: forming on a substrate a first conductive layer made of silicon film having a micro roughness caused by the grains of silicon on its surface; forming a dielectric film on the surface of said micro roughness of said silicon film; and forming a second conductive layer on said dielectric film.
Claim 2
Dependent Claim
37 words
A method as claimed in claim 1, wherein the step of forming said first conductive layer includes a process of depositing silicon at a temperature where silicon makes transition from a amorphous phase to a polycrystalline phase.
Claim 3
Dependent Claim
19 words
A method as claimed in claim 2, wherein said transition temperature lies in a range of 580 to 600°C.
Claim 4
Dependent Claim
52 words
A method as claimed in claim 2, wherein the step of forming said first conductive layer includes a process of forming an amorphous silicon layer on said substrate and a process of annealing said amorphous silicon layer at a temperature above the transition temperature from the amorphous phase to the polycrystalline phase.
Claim 5
Dependent Claim
29 words
A method as claimed in claim 4 further comprising a process of cleaning the surface of said amorphous silicon layer prior to subjecting the sample to said annealing process.
Claim 6
Dependent Claim
26 words
A method as claimed in claim 1, wherein size of said grains of silicon is in a range of 300 to 1700 angstroms in a diameter.
References Cited (Backward Citations)
US4905072A
Cited
DE3915594A1
Cited
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