EP0448069A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Diversity circuit and frame phase (or sampling timing) estimation circuit using the diversity circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1991-03-20
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Granted: —
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Expires: 2011-03-20
Abstract
Abstract A diversity circuit is disclosed which includes CIR estimation circuits (31,32), error computers (33,34) for computing the ratios of the estimated CIR power to the error power between the estimated and actual received signal for respective received signals, (12,13) a comparator (10) for comparing respective ratios, and a selector (11) for outputting the received signal (15) and the CIR (16) corresponding to the maximum power ratio. A frame phase (or sampling timing) estimation circuit using the diversity circuit further includes a delay circuit (21) for providing a received signal with different delays, whereby the selector (11) outputs the delayed received signal (15) and the CIR (16) corresponding to the maximum power ratio.
Inventors
- 👤 Hiroshi C/O Tsushin System Kenkyusho Kubo
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 20:55
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/02; H04L1/06; H04L25/00; H04L25/02; H04L25/0202; H04L25/0204; H04L25/0212
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
261 words
A diversity circuit having a plurality of input terminals and receiving at the respective input terminals respective received signals which have been propagated through different signal paths, said diversity circuit comprising: transmission channel characteristic estimation circuits provided to correspond to said plurality of input terminals, each of said transmission channel characteristic estimation circuits estimating the characteristics of the transmission channel of each signal path on the basis of each of said received signals to output the estimated value of the transmission channel characteristics; error computing circuits provided to correspond to said respective transmission channel characteristic estimation circuits, each of said error computing circuits computing the power of the estimated transmission channel characteristics on the basis of said estimated value which is output from the corresponding transmission channel characteristic estimation circuit, and estimating a received signal on the basis of said corresponding estimated value and the transmission pattern which is known in advance, to compute the power ratio of the power of said estimated transmission channel characteristics to the corresponding error power between the power of the estimated received signal and the power of said received signal; a comparison circuit for comparing the respective power ratios respectively output from said error computing circuits, to output the selection signal designating the signal path corresponding to the maximum power ratio; and a selection circuit for outputting the received signal and the estimated value of the transmission channel, which correspond to said signal path designated by said relation signal, out of said respective received signals and said respective estimated values of the transmission channel characteristics.
Claim 2
Dependent Claim
193 words
A diversity circuit for receiving a plurality of received signals which have been propagated through a plurality of different signal paths and for selecting an optimum received signal, said diversity circuit comprising: transmission channel characteristic estimation means for computing the estimated value of the transmission channel characteristics representing the estimated characteristics of the transmission channel of the signal path on the basis of the received signal, for each of said plurality of received signals; means for computing the power of the estimated transmission channel characteristics on the basis of said estimated value for each received signal; means for estimating a received signal on the basis of said estimated value and the transmission pattern which is known in advance, for each received signal; means for computing the error power between the power of the estimated received signal and the power of said corresponding received signal for each received signal; means for computing the power ratio of said power of the estimated transmission channel characteristics to said corresponding error power for each received signal; and means for comparing respective power ratios and for selecting and outputting the received signal corresponding to the maximum power ratio.
Claim 3
Dependent Claim
41 words
A diversity circuit as defined in Claim 2, wherein said means for selecting and outputting the received signal corresponding to the maximum power ratio further selects and outputs the estimated value of the transmission channel corresponding to the maximum power ratio.
Claim 4
Dependent Claim
18 words
A diversity circuit as defined in Claim 2, wherein said transmission channel characteristics comprise a channel impulse response.
Claim 5
Dependent Claim
55 words
A diversity circuit as defined in Claim 2, wherein said transmission channel characteristic estimation means, said means for computing the power of the estimated transmission channel characteristics, said means for estimating a received signal, said means for computing the error power, and said means for computing the power ratio are provided to respective received signals.
Claim 6
Dependent Claim
270 words
A frame phase (or sampling timing) estimation circuit using a diversity circuit, comprising: a delay circuit for providing a received signal with a plurality of different delays to output a plurality of differently delayed received signals, said diversity circuit including: transmission channel characteristic estimation circuits provided to correspond to said plurality of differently delayed received signals, each of said transmission channel characteristic estimation circuits estimating the transmission channel characteristics on the basis of each of said plurality of differently delayed received signals to output the estimated value of the transmission channel characteristics; error computing circuits provided to correspond to said respective channel characteristic estimation circuits, each of said error computing circuits computing the power of the estimated transmission channel characteristics on the basis of said estimated value which is output from the corresponding transmission channel characteristic estimation circuit, and estimating a received signal on the basis of said corresponding estimated value and the transmission pattern which is known in advance, to compute the power ratio of the power of said estimated transmission channel characteristics to the corresponding error power between the power of the estimated received signal and the power of said received signal; a comparison circuit for comparing the respective power ratios respectively output from said error computing circuits, to output the selection signal designating the delay corresponding to the maximum power ratio; and a selection circuit for outputting the delayed received signal and the estimated value of the transmission channel, which correspond to said delay designated by said selection signal, out of said plurality of differently delayed received signals and said respective estimated values of the transmission channels.
Claim 7
Dependent Claim
197 words
A frame phase (or sampling timing) estimation circuit using a diversity circuit, comprising: a delay circuit for providing a received signal with a plurality of different delays to output a plurality of differently delayed received signals, said diversity circuit including: transmission channel characteristic estimation means for computing the estimated value of the transmission channel characteristics on the basis of each of said plurality of differently delayed received signals; means for computing the power of the estimated transmission channel characteristics on the basis of said estimated value for each differently delayed received signal; means for estimating a received signal on the basis of said estimated value and the transmission pattern which is known in advance, for each differently delayed received signal; means for computing the error power between the power of the estimated received signal and the power of said corresponding delayed received signal for each differently delayed received signal; means for computing the power ratio of said power of the estimated transmission channel characteristics to said corresponding error power for each differently delayed received signal; and means for comparing respective power ratios and for selecting and outputting the delayed received signal corresponding to the maximum power ratio.
Claim 8
Dependent Claim
46 words
A frame phase (or sampling timing) estimation circuit as defined in Claim 7, wherein said means for selecting and outputting the received signal corresponding to the maximum power ratio further selects and outputs the estimated value of the transmission channel corresponding to the maximum power ratio.
Claim 9
Dependent Claim
23 words
A frame phase (or sampling timing) estimation circuit as defined in Claim 7, wherein said transmission channel characteristics comprise a channel impulse response.
Claim 10
Dependent Claim
60 words
A frame phase (or sampling timing) estimation circuit as defined in Claim 7, wherein said transmission channel characteristic estimation means, said means for computing the power of the estimated transmission channel characteristics, said means for estimating a received signal, said means for computing the error power, and said means for computing the power ratio are provided to respective received signals.
References Cited (Backward Citations)
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