EP0448048A2
Expired / Lapsed
EP
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A signal detecting circuit for detecting a signal specified in a designated frequency
Assignee: Fujitsu Ltd
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Filing: 1991-03-19
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Granted: —
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Expires: 2011-03-19
Abstract
Abstract A designated burst signal specified in a designated frequency is detected from an all-inclusive signal (S i ) specified in a plurality of frequencies, by multiplying a frequency of the all-inclusive signal (S i ) by a multiplying factor so as to produce a multiplied output signal (S33), performing a phase-lock loop operation between the multiplied output signal (S33) and an oscillated signal produced for performing the phase-lock loop operation and specified in a multiplied frequency of the designated frequency by the multiplying factor, so as to produce a phase-lock output signal (S41) and comparing the multiplied output signal (S33) and the phase-lock output signal (S41) for producing a detected output signal (S d ) representing whether the designated burst signal is in the all-inclusive signal.
Inventors
- 👤 Toshiyuki Sato
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 20:39
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/095; H03D; H03D3/00; H03D3/02; H03D3/24; H03D3/241; H03B; H03B19/00; H03B19/16; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
222 words
A signal detecting circuit for detecting a designated signal specified in a designated frequency, from an input signal, specified in a plurality of frequencies, to the signal detecting circuit, said signal detecting circuit comprising: a frequency multiplier for multiplying an input frequency, which is one of the plurality of frequencies, of the input signal, said frequency multiplier having a multiplying factor and producing a multiplier output signal specified in a frequency obtained by multiplying the input frequency by the multiplying factor; a phase-lock loop circuit for performing phase-lock between a phase of the multiplier output signal and a phase of an oscillation signal produced in said phase-lock loop circuit and producing a phase-lock output signal, said oscillation signal being specified in a multiplied frequency of the designated frequency by the multiplying factor and said phase-lock being performed by comparing phases of the multiplier output signal and the oscillation signal, producing a comparison result and shifting the phase of the oscillation signal in response to the comparison result so that the phases of the multiplier output signal and the oscillation signal are synchronized with each other; and a phase-lock detector for producing a detected output signal of the signal detecting circuit for representing whether the designated signal is in the input signal, by comparing the multipier output signal with the phase-lock output signal.
Claim 2
Dependent Claim
39 words
A signal detecting circuit according to claim 1, wherein said frequency multiplier comprises a diode bridge circuit performing fullwave rectification of the input signal for producing a multiplier output signal specified in a doubled frequency of the input frequency.
Claim 3
Dependent Claim
56 words
A signal detecting circuit according to claim 2, wherein said frequency multiplier further comprises: a low pass filter for extracting a filter output signal specified in the doubled frequency, from the multipier output signal specified in the doubled frequency; and a waveform shaper for shaping a waveform of the filter output signal into a rectangle-shaped wave.
Claim 4
Dependent Claim
173 words
A signal detecting method for detecting a designated signal specified in a designated frequency from an all-inclusive signal to be examined, specified in a plurality of frequencies; said method comprising the steps of: multiplying a frequency of the all-inclusive signal by a multiplying factor, producing a multiplied signal specified in a multiplied frequency of the frequency of the all-inclusive signal by the multiplying factor; comparing a phase (first phase) of the multiplied signal with a phase (second phase) of an oscillated signal specified in a multiplied frequency of the designated frequency by the multiplying factor, producing a comparison output signal; shifting the second phase in response to the comparison output signal so that the first phase is locked with the second phase; repeating said steps of phase comparison and phase shift until phase-lock between the first and second phases is established and producing a phase-lock output signal; and comparing the phase-lock output signal with the multiplying signal for producing a detected output signal representing whether the designated signal is in the all-inclusive signal.
References Cited (Backward Citations)
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