EP0447242A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor integrated circuit device having output stabilizing means
Assignee: Fujitsu Ltd
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Filing: 1991-03-14
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Granted: —
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Expires: 2011-03-14
Abstract
Abstract A semiconductor integrated circuit device includes a memory cell array (28), an addressing part (21, 22, 24, 25), and a detection circuit (27) for detecting a change in an address signal and for outputting an ATD pulse having a predetermined pulse width when the change is detected. The device also includes a sense amplifier (30) for amplifying information read out from the memory cell array and for outputting an amplified information signal, and an output part (91, 191A) for setting an output terminal (OUT) to either a first level or a second level in response to the amplified information signal. Further, the device includes an intermediate level generating circuit (75, 93; 191B) for setting the output terminal to an intermediate level during a period corresponding to the pulse width of the ATD pulse, the intermediate level being lower than the first level and higher than the second level.
Inventors
- 👤 Kouji Ueno
- 👤 Yuji Tsuchimoto
- 👤 Yoshikazu Mutoh
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 17:03
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; G11C7/1069
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
207 words
A semiconductor integrated circuit device including: a memory cell array (28) having a plurality of memory cells; addressing means (21, 22, 24, 25), coupled to said memory cell array, for decoding an address signal supplied from an external device and for outputting a decoded address to said memory cell array, information related to said decoded address being read out from said memory cell array; detection means (27) for detecting a change in a predetermined signal and for outputting a detection pulse (ATD) having a predetermined pulse width when said change is detected; sense amplifier means (30), coupled to said memory cell array, for amplifying said information and for outputting an amplified information signal; and output means (91; 191A) for setting an output terminal (OUT) to either a first level (V OH ) or a second level (V OL ) in response to said amplified information signal, characterized in that said semiconductor integrated circuit device comprises intermediate level generating means (75, 93; 191B), coupled to said detection means and said output terminal, for setting said output terminal to an intermediate level during a period corresponding to said pulse width of said detection pulse, said intermediate level being lower than said first level and higher than said second level.
Claim 2
Dependent Claim
158 words
A semiconductor integrated circuit device as claimed in claim 1, characterized in that said output means comprises: a first transistor (72) having a collector coupled to a first power supply line (Vcc), an emitter coupled to said output terminal, and a base; a second transistor (74) having a collector coupled to said output terminal, an emitter coupled to a second power supply line (GND), and a base; and a third transistor (92) having a collector coupled to the base of said first transistor, an emitter coupled to the base of said second transistor, and a base coupled to said sense amplifier means, and that said intermediate level generating means comprises control means (75, 93) for generating a base potential of said first transistor from a power supply voltage (GND) via said second power supply line during said period so that a slight current passes from said first power supply line to said output terminal through said first transistor.
Claim 3
Dependent Claim
91 words
A semiconductor integrated circuit device as claimed in claim 2, said control means comprises: level shift means (93, 95) for generating a predetermined level from said power supply voltage via said second power supply line, said predetermined level causing said first transistor to pass said slight current and being applied, as said base potential of said first transistor, to the base of said first transistor; and switching means (75) for connecting said level shift means coupled to the base of said first transistor said second power supply lines during said period.
Claim 4
Dependent Claim
43 words
A semiconductor integrated circuit device as claimed in claim 3, characterized in that said level shift means comprises at least one level shift diode having an anode coupled to the base of said first transistor and a cathode coupled to said switching means.
Claim 5
Dependent Claim
41 words
A semiconductor integrated circuit device as claimed in claim 4, characterized in that said output means (91) comprises a diode (96) having an anode coupled to said output terminal and a cathode coupled to the cathode of said level shift diode.
Claim 6
Dependent Claim
47 words
A semiconductor integrated circuit device as claimed in claim 3, characterized in that said switching means comprises a fourth transistor (75) having a collector coupled to said level shift means, an emitter coupled to said second power supply line, and a base controlled by said detection pulse.
Claim 7
Dependent Claim
43 words
A semiconductor integrated circuit device as claimed in claim 2, characterized in that said output means comprises high-impedance setting means (76, 77) for turning OFF said third transistor (92) during said period so that said output terminal is set to a high-impedance state.
Claim 8
Dependent Claim
29 words
A semiconductor integrated circuit device as claimed in any of claims 1 to 7, characterized in that said first, second and third transistors (72, 74, 92) are bipolar transistors.
Claim 9
Dependent Claim
100 words
A semiconductor integrated circuit device as claimed in claim 1, characterized in that: said output means comprises a transistor (72) having a collector coupled to a first power supply line (Vcc), an emitter coupled to said output terminal, and a base, and that said intermediate level generating means (75, 93) comprises control means (75, 93) for generating a base potential of said first transistor from a power supply voltage (GND) via a second power supply line (GND) during said period so that a slight current passes from said first power supply line to said output terminal through said first transistor.
Claim 10
Dependent Claim
39 words
A semiconductor integrated circuit device as claimed in claim 9, characterized in that said output means comprises a Schottky diode (79) having an anode coupled to the emitter of said transistor, and a cathode coupled to said output terminal.
Claim 11
Dependent Claim
134 words
A semiconductor integrated circuit device as claimed in claim 1, characterized in that: said output means comprises CMOS inverter means (191A) for receiving said amplified information signal and for setting said output terminal to one of said first level and said second level in response to said amplified information signal, and that said intermediate level generating means (191B) comprises: a first transistor (Tr2) having a collector coupled to a first power supply line (Vcc), an emitter coupled to said output terminal, and a base; and control means (D1-D3, Tr1) for generating a base potential of said first transistor from a power supply voltage (GND) via a second power supply line (GND) during said period so that a slight current passes from said first power supply line to said output terminal through said first transistor.
Claim 12
Dependent Claim
99 words
A semiconductor integrated circuit device as claimed in claim 11, characterized in that said intermediate level generating means (191B) comprises: level shift means (D1-D3) for generating a predetermined level from said power supply voltage (GND) via said second power supply line, said predetermined level causing said first transistor to pass said slight current and being applied, as said base potential of said first transistor, to the base of said first transistor; and switching means (Tr1) for connecting said level shift means coupled to the base of said first transistor to said second power supply line (GND) during said period.
Claim 13
Dependent Claim
44 words
A semiconductor integrated circuit device as claimed in claim 12, characterized in that said level shift means comprises at least one level shift diode (D1-D3) having an anode coupled to the base of said first transistor and a cathode coupled to said switching means.
Claim 14
Dependent Claim
40 words
A semiconductor integrated circuit device as claimed in claim 13, characterized in that said output means comprises a diode (D4) having an anode coupled to said output terminal and a cathode coupled to the cathode of said level shift diode.
Claim 15
Dependent Claim
47 words
A semiconductor integrated circuit device as claimed in claim 12, characterized in that said switching means comprises a second transistor (Tr1) having a collector coupled to said level shift means, an emitter coupled to said second power supply line, and a base controlled by said detection pulse.
Claim 16
Dependent Claim
51 words
A semiconductor integrated circuit device as claimed in claim 11, characterized in that said output means comprises high-impedance setting means (101, 105, 108-111) for turning OFF said first transistor and for making said CMOS inverter means inactive during said period so that said output terminal is set to a high-impedance state.
Claim 17
Dependent Claim
21 words
A semiconductor integrated circuit device as claimed in claim 11, characterized in that said first transistor (Tr2) is a bipolar transistor.
Claim 18
Dependent Claim
56 words
A semiconductor integrated circuit as claimed in any of claims 1 to 17, characterized in that: said detection means (72) comprises address change detection means (72) for detecting a change in said address signal; and said detection means outputs said detection pulse (ATD) when said address change detection means detects said change in said address signal.
References Cited (Backward Citations)
No citation records indexed.
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