EP0446001A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Motion vector detection circuit used in hierarchical processing of moving picture signal
Assignee: Victor Company of Japan Ltd
•
Filing: 1991-03-04
•
Granted: —
•
Expires: 2011-03-04
Abstract
Abstract In this motion detection circuit (60/70), in detecting motion vectors by using a block of L x M pixels as a unit between images An and Bn of respective hierarchies in which predetermined sampling operations are implemented to an input image A and a comparative image B at n-stages in both horizontal and vertical directions, motion vectors of adjacent blocks of motion vectors detected at the (i - l) stage are taken into consideration as an initial value of motion vector detection at the i-th stage. This detection circuit (60/70) further comprises a circuit (56,46) for providing the initial value by using image data at the (i - l)-th stage corresponding to motion vectors of the adjacent blocks.
Inventors
- 👤 Takami Niihara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 23:21
CPC Classifications
H; H04; H04N; H04N19/00; H04N19/50; H04N19/503; H04N19/51; H04N19/577; H04N19/523; H04N19/53
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
119 words
A motion vector detection circuit (60/70) wherein, in detecting motion vectors by using a block of L x M pixels as a unit between images An and Bn of respective hierarchies in which predetermined sampling operations are implemented to an input image A and a comparative image B at n-stages in both horizontal and vertical directions, motion vectors of adjacent blocks of motion vectors detected at the (i - l)-th stage are taken into consideration as an initial value of motion vector detection at the i-th stage, characterized in that there is provided a circuit (56,46) for providing said initial value by using image data at the (i - l)-th stage corresponding to motion vectors of said adjacent blocks.
Claim 2
Dependent Claim
147 words
The detection circuit as set forth in claim 1, wherein said detection circuit (60) comprises block readout means (42)(46) for detecting, at three stages, motion vectors of said input image and said comparative image as readout data, three storage means (20,24,28)(10,14,18) for holding motion vectors at said respective stages, matching means (54) for allowing readout data on said input image side and on said comparative image side to be in harmony with each other to determine errors and trial vectors, and vector judgment means (56) for making comparisons between errors of said trial vectors sequentially inputted on the basis of an output from said matching means (54) to judge the compared results to determine a minimum error value and a trial vector corresponding thereto, thus to deliver said minimum error value and said trial vector corresponding thereto to block readout means (46) on said comparative image side.
Claim 3
Dependent Claim
97 words
The detection circuit as set forth in claim 2, wherein said detection circuit (60) further work memories (44,48) on said input image side and said comparative image side connected to frame memory groups (32,30) for storing respective three frames of said input image and said comparative image respectively corresponding to first to third stages on said input image side and said comparative image side to read out data of input images and comparative images of said first to third stages from said frame memory groups on the basis of a command from said block readout means (42,46).
Claim 4
Dependent Claim
57 words
The detection circuit as set forth in claim 3, wherein said detection circuit (60) further comprises pixel readout means (50) provided between said matching means (54) and said work memory (44) on the input image side, and block selection means (52) provided between said matching means (54) and said work memory (48) on said comparative image side.
Claim 5
Dependent Claim
60 words
The detection circuit as set forth in claim 2, wherein said detection circuit (60) further comprises a stage block counter (58) for respectively outputting readout commands to said block readout means (42)(46) on said input image side and said comparative image side in order to read out every stages input images and comparative images of said first to third stages.
Claim 6
Dependent Claim
56 words
The detection circuit as set forth in claim 3, wherein said detection circuit (70) further comprises an over-sample circuit (72 or 74) connected to said work memory (44 or 48) and for implementing data of specific pixels in vertical and horizontal directions corresponding to motion vectors of the third stage of data in said work memory.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.