Method of forming isolation trenches in a semiconductor substrate

Claim 1

A method of forming an isolation trench in a silicon wafer having a predetermined conductivity type dopant concentration, said method comprising the steps of: (a) forming a trench in the silicon wafer, said trench having nearly vertical side walls and a bottom surface; characterized by the steps of (b) selectively forming a silicon layer on one said wall and on a portion of the bottom surface of the trench, said silicon layer having said conductivity type dopant concentration which is greater than the dopant concentration of the silicon wafer; (c) annealing the wafer at a temperature and for a time which are sufficient to drive a part of the dopant from the silicon layer into the silicon wafer; and (d) filling the trench with a dielectric material

Claim 2

A method of forming an isolation trench in a P-type silicon substrate having a predetermined amount of a P=type dopant concentration and an N-type dopant concentration well therein, said method comprising the steps of: (a) forming a trench in the silicon wafer, said trench having near vertical parallel walls and a bottom surface there between, a portion of the bottom surface and at least one each said wall lying in the silicon substrate and the N-type dopant concentration well; characterized by: (b) forming a silicon layer on the walls and the bottom surface of the trench which is lying in the P-type silicon substrate, said silicon layer having a P-type dopant concentration whch is much greater than the P-type dopant concentration in the silicon substrate; (c) annealing the P-type silicon substrate to drive the dopant from the silicon layer into the walls and the bottom of the trench; and (d) filling the trench with a dielectric material.

Claim 6

A method of fabricating a CMOS device on a first conductivity type silicon substrate having a second conductivity type well, said well having near vertical walls, said method comprising the steps of: (a) forming a trench having near vertical walls and a bottom surface separating said walls, said trench also separating a first active region in the substrate from a second active region in the well; (b) selectively forming a first conductivity type silicon layer in the trench, said silicon layer also rounding trench corners, said silicon layer further having first conductivity type concentration which is greater than the concentration of the silicon substrate; (c) annealing the substrate at a temperature and for a time which is sufficient to drive the first conductivity type impurity from the silicon layer into the substrate; (d) filling the trench with a dielectric material; and (e) forming a first-conductivity-type-channel transistor in the second active region and a second-conductivity-type-channel transistor in the first active region.

Claim 8

A method of forming an isolation trench in a silicon substrate having a predetermined amount of P-type dopant concentration, said method comprising the steps of: (a) forming a trench in the silicon substrate, said trench having near vertical walls and a nearly flat bottom area separating the trench walls; (b) forming an oxide layer on selected portions of the walls and the bottom area of the trench; (c) exposing the silicon substrate to anhydrous hydrogen chloride (HCL) gas and thereater adding to the HCL a mixture of dichlorosilane and diborane in hydrogen at a predetermined temperature and for a predetermined time to controllably grow a silicon layer of a predetermined thickness, said diborane doping the silicon layer with a P-type impurity concentration that is greater than the P-type dopant concentration of the silicon substrate; (d) driving some of the P-type dopant concentration from the silicon layer to the silicon substrate; and (e) filling the trench with an oxide to obtain a planar silicon substrate surface having the shallow trench.