Controlled silicon doping of III-V compounds by thermal oxidation of silicon capping layer

Claim 1

A method of fabricating a semiconductor device comprising the steps of: depositing a layer of silicon (12) on a surface of a semiconductor substrate (10) of a III-V compound; and thermally oxidizing said silicon layer (12) thereby diffusing silicon into at least a portion of said substrate (10).

Claim 4

The method of one or more of the preceding claims 1 to 3 wherein said silicon is diffused into said substrate (10) to a thickness of about 20 nm or greater with an electron concentration that can be varied up to about 1x10¹⁹ cm⁻³.

Claim 5

The method of one or more of the preceding claims 1 to 4 wherein said thermal oxidizing step is performed in an atmosphere of one of pure O₂, dry air, steam and diluted O₂ in an inert carrier gas, preferably the oxidizing atmosphere is diluted O₂ in Ar having a oxygen concentration of about 200 ppm or greater.

Claim 6

The method of one or more of the preceding claims 1 to 5 wherein said thermal oxidizing step is performed at a temperature in the range of about 500 to 1100°C.

Claim 7

The method of one or more of the preceding claims 1 to 6 wherein the oxidizing step is performed by rapid thermal oxidation.

Claim 8

The method of one or more of the preceding claims 1 to 7 further including the step of annealing said substrate (10) subsequent to said thermal oxidizing step sufficient to cause at least a portion of said substrate (10) having the diffused silicon (14) to have a sheet resistance lower than the sheet resistance of said portion after the thermal oxidizing step.

Claim 11

The method of one or more of the preceding claims 8 to 10 wherein said annealing step is performed in an inert atmosphere at a temperature of about 600°C or greater.

Claim 12

The method of one or more of the preceding claims 8 to 11 wherein said thermal oxidation step and said annealing step are performed in situ.

Claim 13

The method of one or more of the preceding claims 8 to 12 wherein said thermal oxidizing step is performed under oxidizing conditions including type of oxygen ambient, amount of oxygen in the ambient, temperature and time of said step and wherein said annealing step is performed under annealing conditions including type of ambient, temperature and time and further including the step of controlling the sheet resistance and depth of the diffused silicon (14) by controlling the thickness of said silicon (14), the oxidizing conditions and the annealing conditions.

Claim 14

The method of one or more of the preceding claims 1 to 13, further including the step of depositing a barrier layer (18) on said III-V compound substrate (10) prior to the deposition of said silicon layer (12).

Claim 16

The method of one or more of the preceding claims 1 to 15 further including the step of doping said silicon layer (12) prior to the thermal oxidizing step with one of phosphorus, arsenic and boron.

Claim 17

The method of one or more of the preceding claims 1 to 16 further including the step of forming an ohmic contact to the at least a portion of said substrate (10) having the silicon diffusion (14) by removing the oxide layer, depositing a layer of metal on the silicon layer (12) and annealing the silicon (12) and metal layers to provide a low resistivity contact to the portion of the substrate (10) having the diffused silicon (14) therein.

Claim 18

A method for forming a MESFET comprising the steps of: depositing a first layer of silicon (22) on a surface of a semiconductor substrate (21) of a III-V compound; thermally oxidizing said first silicon layer (22) thereby diffusing silicon into at least a portion of said substrate (21) at temperatures and oxidizing conditions to form a shallow channel diffusion region (20); removing said silicon layer; depositing at least one metal gate (24) on the substrate (21); depositing a second layer of silicon (26) on the substrate (21) and said at least one metal gate (24); thermally oxidizing said second silicon layer (26) thereby diffusing silicon into said substrate (21) adjacent said at least one metal gate (24) at temperatures and oxidizing conditions to form silicon diffusion source and drain regions (30); and removing said second silicon layer (26) forming ohmic contacts to said source and drain regions (30).

Claim 19

A method for forming a MESFET comprising the steps of: depositing at least one pad of silicon oxinitride (42) on the surface of a semiconductor substrate (40) of a III-V compound; depositing a conformal layer of silicon (44) on the surface of said substrate (40) and said pads (42); thermally oxidizing said silicon layer (44) thereby diffusing silicon into said substrate (40) at temperatures and oxidizing conditions to form a channel region (48) below said at least one pad (42) and source and drain regions (46) adjacent said pad (42); removing said silicon layer (44) and said at least one pad (42); depositing a gate region (54) on the substrate (40) above said channel region (48); and forming ohmic contacts (52) to said source and drain regions (46).