Sense circuit for non-volatile memory device

Claim 1

A sense circuit for a non-volatile memory device which includes a plurality of cell transistors (Q6) which form memory cells, each cell transistor being connected to one of a plurality of word lines (10, WL) and to one of a plurality of bit lines (BL), said bit lines being connected to a bus line (N2), said sense circuit comprising selecting means (Q5) coupled to the bus line for selecting a predetermined cell transistor by selecting a predetermined bit line which is connected to the predetermined cell transistor; a feedback type bias circuit (Q1, Q2, Q4) coupled to said selecting means for maintaining a potential of the bus line to a constant level, said feedback type bias circuit including a first transistor (Q4) which flows a current to the bus line; and detecting means (Q3, Q7, Q8, Q10) coupled to said feedback type bias circuit for detecting whether or not a current flows through the predetermined cell transistor so as to read a data from the predetermined cell transistor, said detecting means including a terminal (11) for outputting the read data, characterized in that there is provided : current source means (Q9) coupled to said feed back type bias circuit (Q1, Q2, Q4) and including a second transistor (Q9) for forcibly supplying a predetermined current to said first transistor (Q4), so that a gate-source voltage of said first transistor is greater than a threshold voltage of said first transistor.