EP0443239A1
Expired / Lapsed
EP
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Current mirror with base current compensation
Assignee: Precision Monolithics Inc
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Filing: 1990-09-10
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Granted: —
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Expires: 2010-09-10
Abstract
Abstract A current mirror circuit with master (T1) and slave bipolar transistors (T2, T3) has an insulated gate field effect transistor (FET) (M1) connected across the collector-base circuit of the master transistor (T1) to provide base compensation current for the various bipolar transistors (T1, T2, T3). The FET (M1) is scaled so that the collector-emitter voltage of the master transistor (T1) is set at a value at which it operates in the vicinity of its saturated region, and the collector-base voltages of the master (T1) and slave transistors (T2, T3) are generally equal. This results in an accurate mirroring of the master transistor (T1) current, while the current through the master transistor (T1) is itself preserved at the desired reference level because the FET (M1) does not draw any gate current away from the master transistor (T1).
Inventors
- 👤 Douglas S. Smith
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 13:16
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/267
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
84 words
A base current compensated current mirror circuit comprising: a master bipolar transistor (T1) and at least one slave bipolar transistor (T2, T3) having a common base connection with the master transistor (T1) in a current mirror configuration and proportionately matched with said master transistor (T1), and an insulated gate field effect transistor (FET) (M1) having a gate connected to the collector of the master bipolar transistor (T1), and a source-drain circuit connected to provide a base current compensation current to said common base connection.
Claim 2
Dependent Claim
33 words
The current mirror circuit of claim 1, wherein said insulated gate FET (M1) is geometrically scaled so that the collector-base voltages of the master (T1) and slave transistors (T2, T3) are generally equal.
Claim 3
Dependent Claim
44 words
The current mirror circuit of claim 1, wherein said insulated gate FET (M1) is geometrically scaled to establish the collector-emitter voltages of the master (T1) and slave transistors (T2, T3) at values at which said transistors operate in the vicinity of their saturated regions.
Claim 4
Dependent Claim
34 words
The current mirror circuit of claim 3, wherein said insulated gate FET (M1) is geometrically scaled to establish the collector-emitter voltage of the master (T1) and slave transistor (T2, T3) at approximately 2-3 volts.
Claim 5
Dependent Claim
129 words
A base current compensation current mirror circuit, comprising: a master bipolar transistor (T1) and at least one slave bipolar transistor (T2, T3) having a common base connection with the master transistor (T1) in a current mirror configuration and proportionately matched with said master transistor (T1), a current source (2) connected to supply a reference current (I REF ) to the collector-emitter circuit of said master transistor (T1), a voltage supply (V+), and an insulated gate field effect transistor (FET) (M1) having a gate connected to the collector of the master bipolar transistor (T1), and a source-drain circuit connected between said voltage supply (V+) and said common base connection, said FET (M1) being configured to substantially supply the base currents of said master (T1) and slave bipolar transistors (T2, T3).
Claim 6
Dependent Claim
33 words
The current mirror circuit of claim 5, wherein said insulated gate FET (M1) is geometrically scaled so that the collector-base voltages of the master (T1) and slave transistors (T2, T3) are generally equal.
Claim 7
Dependent Claim
44 words
The current mirror circuit of claim 5, wherein said insulated gate FET (M1) is geometrically scaled to establish the collector-emitter voltages of the master (T1) and slave transistors (T2, T3) at values at which said transistors operate in the vicinity of their saturated regions.
Claim 8
Dependent Claim
34 words
The current mirror circuit of claim 7, wherein said insulated gate FET (M1) is geometrically scaled to establish the collector-emitter voltages of the master (T1) and slave transistors (T2, T3) at approximately 2-3 volts.
Claim 9
Dependent Claim
65 words
The current mirror circuit of claim 5, further comprising respective resistors (R1, R2, R3) connected to the collector-emitter circuits of said master (T1) and slave bipolar transistors (T2, T3), the resistance values of said resistors (R1, R2, R3) being generally inverse to the intended scalings of their respective bipolar transistors (T1, T2, T3) to at least partially compensate for manufacturing tolerances in said transistor scalings.
References Cited (Backward Citations)
US4008441A
Cited
US4673867A
Cited
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