§
Luxuse
Patent Intelligence
Sign In
← Back to Patent Explorer
EP0442561A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Semiconductor relay circuit

Assignee: Panasonic Electric Works Co Ltd
•
Filing: 1991-02-05
•
Granted: —
•
Expires: 2011-02-05
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A semiconductor relay circuit includes a MOS FET (14) receiving a photovoltaic output generated across a photovoltaic diode array (13) responsive to a light signal from a light-emitting element (12), across gate and source electrodes (15,15a) of which MOS FET a control circuit (16) is connected to be at a high impedance state during the generation of the photovoltaic output but to be at a low impedance state upon disappearance of the output, and resistors (17,18) are inserted in series respectively in each of a path flowing a current from the photovoltaic diode array across the gate and source electrodes of the MOS FET and a path flowing a discharge current from a capacity across the gate and source electrodes of the MOS FET to the control circuit, whereby the setting of rise and fall of circuit output signals can be made easier.

Inventors

  • 👤 Yukio Idaka
  • 👤 Shuichiroh Yamaguchi
  • 👤 Hisakazu Miyajima
  • 👤 Takeshi Matsumoto
  • 👤 Yasunori Miyamoto

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-01 15:15
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/78; H03K17/785; H10; H10F; H10F55/00; H10F55/20; H10F55/25; H10F55/255; Y; Y10; Y10S; Y10S136/00; Y10S136/291; Y10S136/293

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 174 words
A semiconductor relay circuit in which a photovoltaic diode array is optically coupled to a light-emitting element to receive a light signal generated by said element upon presence of an input current thereto and to generate a photovoltaic output, an output MOS FET is connected to said photovoltaic diode array to vary from a first impedance state to a second impedance state upon application of the photovoltaic output across gate and source electrodes of said MOS FET, and a control means which is in a high impedance state upon generation of the photovoltaic output but in a low impedance state upon disappearance of the photovoltaic output is connected across the gate and source electrodes of the MOS FET, characterized in that resistors are inserted in series with respect to a path flowing a charge current from the photovoltaic diode array across the gate and source electrodes of said MOS FET and a path flowing a discharge current from a capacity across the gate and source electrodes of the MOS FET to the control means.
Claim 2
Dependent Claim 33 words
A circuit according to claim 1, wherein said resistors comprise a first resistor inserted in said path flowing said charge current and a second resistor inserted in said path flowing said discharge current.
Claim 3
Dependent Claim 39 words
A circuit according to claim 2, wherein a rectifying element is connected in parallel with said second resistor to be in normal direction with respect to said charge current but in reverse direction with respect to said discharge current.
Claim 4
Dependent Claim 79 words
A circuit according to claim 3, wherein said rectifying element comprises a PN junction between a first semiconductor layer of one conduction type on a semiconductor substrate and a second semiconductor layer of the other conduction type formed on said first semiconductor layer, said second semiconductor layer being connected at an end to said first semiconductor layer, and said second resistor comprises said second semiconductor layer made parallel to said rectifying element upon reverse biasing of the rectifying element.
Claim 5
Dependent Claim 41 words
A circuit according to claim 2, wherein a voltage responsive element is connected in parallel with said second resistor and to be in a low impedance state with respect to said discharge current and with a voltage above a predetermined level.
Claim 6
Dependent Claim 26 words
A circuit according to claim 5, wherein said voltage responsive element comprises an NMOS FET of an enhancement mode and having drain and gate electrodes short-circuited.

References Cited (Backward Citations)

US4804866A Cited
FR2602620A1 Cited

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag