EP0442041A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Integrated digital signal processor/general purpose CPU with shared internal memory
Assignee: National Semiconductor Corp
•
Filing: 1990-10-31
•
Granted: —
•
Expires: 2010-10-31
Abstract
Abstract An integrated data processing platform for processing a digital signal that includes a general purpose processor and a digital signal processor (DSP) module. The DSP module recovers digital data from a digital signal utilizing a sequence of DSP operations selected by the general purpose processor. The general purpose processor processes the digital data recovered by the DSP module, but is also available to perform general purpose tasks. A shared internal memory array selectively provides information to the DSP module and to the general purpose processor. The information stored in the internal memory array includes operands utilized in the execution of the DSP algorithm and selected instructions and data utilized by the general purpose CPU either for controlling the execution of the DSP algorithm or for executing its own general purpose tasks. While in many applications the data processing system will include an analog front end that converts a modulated input signal received on an analog transmission channel to a corresponding digital signal for processing by the data processing system, the data processing system may also receive the digital signal directly from a digital source.
Inventors
- 👤 Amos Intrater
- 👤 Moshe Doron
- 👤 Gideon Intrater
- 👤 Lev Epstein
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 02:56
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; H; H04; H04L; H04L27/00; G06F15/76; G06F15/78; G06F15/7839; G06F15/7842; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
62 words
An integrated data processing platform for processing a digital signal, the data processing platform comprising: a) digital signal processor (DSP) for processing the digital signal by executing a DSP algorithm; b) a general purpose processor for controlling the digital signal processor; and c) a shared internal memory array that is accessible by both the digital signal processor and the general purpose processor.
Claim 2
Dependent Claim
128 words
An integrated data processing platform for processing a digital signal, the data processing platform comprising: a) an internal bus; b) a digital signal processor (DSP) module, connected to the internal bus, for recovering digital data from the digital signal by executing a DSP algorithm; c) a general purpose processor, connected to the internal bus, for controlling the DSP module and for processing the digital data recovered by the DSP module; and d) an internal memory array connected to the internal bus such that the internal memory array is accessible by both the DSP module and the general purpose processor for selectively providing operands stored in the internal memory array to the DSP module and instructions and data stored in the internal memory array to the general purpose processor.
Claim 3
Dependent Claim
43 words
An integrated data processing platform as in Claim 2 and further including an analog front end that converts a modulated input signal received by the analog front end from an analog channel to the digital signal for processing by the data processing platform.
Claim 4
Dependent Claim
25 words
An integrated data processing platform as in Claim 2 wherein the digital signal is received by the data processing platform directly from a digital source.
Claim 5
Dependent Claim
148 words
A data processing system for processing a digital signal, the data processing system comprising: a) a digital signal processor (DSP) that recovers digital data from the digital signal by executing a selected sequence of DSP operations; b) a general purpose processor that selects the sequence of DSP operations for execution by the digital signal processor from a set of basic DSP operations and that performs general purpose processing tasks utilizing selected instructions and data; c) an internal bus to which both the digital signal processor and the general purpose central processing unit are connected; and d) an internal memory array connected to the internal bus such that the internal memory array is accessible by the digital signal processor for retrieving operands utilized by the digital signal processor in executing the selected sequence of DSP operations and by the general purpose processor for retrieving the selected instructions and data.
Claim 6
Dependent Claim
43 words
A data processing system as in Claim 5 and further including a bus interface unit connected between the internal bus and an external system memory for implementing the transfer of operands, instructions and data between the internal bus and the external system memory.
Claim 7
Dependent Claim
47 words
A data processing system as in Claim 6 wherein the digital signal processor includes an internal address generator connected to the internal memory array for retrieving operands from the internal memory array for use by the digital signal processor in executing the selected sequence of DSP operations.
Claim 8
Dependent Claim
35 words
A data processing system as in Claim 5 and further including an analog front end that converts a modulated input signal received by the analog front end from an analog channel to the digital signal.
Claim 9
Dependent Claim
24 words
A data processing system as in Claim 5 wherein the digital signal is received by the data processing system directly from a digital source.
Claim 10
Dependent Claim
167 words
An improved data processing system that includes a general purpose processor connected to a bus interface unit via an internal bus for retrieving instructions and data from an external memory via the bus interface unit and an internal memory array connected to the internal bus for providing internal storage for instructions and data retrieved by the general purpose processor from the external memory, the improvement comprising a digital signal processor (DSP) module connected to the internal bus such that the internal memory array is accessible to both the general purpose processor and the DSP module, the DSP module comprising: (a) a control register for storing a DSP command issued to the DSP module by the general purpose processor via the internal bus; (b) multiplier/accumulator means responsive to storage of the DSP command in the control register for initiating execution of a DSP operation corresponding to the DSP command; and (c) address generator means for referencing operands for utilization by the multiplier/accumulator means in executing the DSP operation.
Claim 11
Dependent Claim
36 words
A data processing system as in claim 10 wherein the multiplier/accumulator means includes first and second input ports for receiving first and second operands, respectively, for utilization by the multiplier/accumulator means in executing the DSP operation.
Claim 12
Dependent Claim
22 words
A data processing system as in claim 11 wherein the address generator means includes means for retrieving the first and second operands.
Claim 13
Dependent Claim
27 words
A data processing system as in claim 10 wherein the address generator means includes means for retrieving the first and second operands from the internal memory array.
Claim 14
Dependent Claim
41 words
A data processing system as in claim 11 wherein the address generator means includes means for retrieving the first operand from the internal memory array and means for retrieving a second operand from the external memory via the bus interface unit.
Claim 15
Independent Claim
127 words
A method for processing a digital signal, the method comprising: (a) selecting from a set of digital signal processor (DSP) operations to define a specific sequence of DSP operations for processing the digital signal; (b) retrieving operands required for execution of the specific sequence of DSP operations by a DSP module and instructions and data required by a general purpose processor for executing a general purpose processor task; (c) loading the operands, instructions and data into a memory array that is accessible by both the general purpose processor and the DSP module; and (d) implementing execution of the specific sequence of basic DSP operations by the DSP module under the control of the CPU by retrieving operands from the memory array for use by the DSP module.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.