EP0440452A2
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EP
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Multiple bus system memory architecture
Assignee: HP Inc
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Filing: 1991-01-30
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Granted: —
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Expires: 2011-01-30
Abstract
Abstract A microcomputer system memory architecture and method allows the system memory (102,202) to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller (308) capable of performing the addressing of the system memory (102,202). The microprocessor (106,206) and the system memory (102,202) communicate via a high speed host bus (104). The system memory (102,202) is comprised of multiple 64-bit system memory buses (1-N; 211,212) to permit high speed data transfer to the microprocessor (106,206) in a burst mode without the need for an external cache. <IMAGE>
Inventors
- 👤 Carol E. Bassett
- 👤 Robert G. Campbell
- 👤 Marilyn J. Lang
- 👤 Sridhar Begur
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 15:42
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0877; G06F12/0879
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
35 words
A system for high speed data access in a microcomputer, comprising: a system memory (102,202) having at least two 64-bit system memory buses (1-N; 211,212) in parallel electrical communication with a 32-bit host bus (104).
Claim 2
Dependent Claim
49 words
A system memory architecture according to claim 1, wherein each said 64-bit system memory buses (1-N; 211-212) comprises two 32-bit bidirectional latching transceivers (211A, 211B, 212A, 212B) situated to read from system memory (202) in parallel and situated to transmit system memory data to said 32-bit host bus (104).
Claim 3
Dependent Claim
36 words
A system memory architecture according to claim 1, wherein said system memory buses (1-N; 211,212) comprise SIMMs (215-220), and said host bus is in direct electrical communication with an 80486-type microprocessor (206) and operates synchronously therewith.
Claim 4
Dependent Claim
23 words
A microcomputing system according to claim 3, wherein said system memory buses (1-N; 211,212) comprise static column DRAMs situated on said SIMMs (215-220).
Claim 5
Dependent Claim
25 words
A microcomputing system according to any of claims 1 to 4, wherein said system memory buses (1-N; 211,212) operate synchronously with said host bus (104).
Claim 6
Dependent Claim
38 words
A microcomputing system according to any of claims 1 to 5, wherein said host bus (104) can access data in said system memory (102,202) with a bandwidth of 50 megabytes per second while operating in said burst mode.
Claim 7
Dependent Claim
20 words
A microcomputing system according to claim 2, wherein said system memory (102,202) is controlled by a system memory controller (308).
Claim 8
Independent Claim
115 words
A method of data retrieval from a system memory (102,202) having at least two parallel 64-bit system memory buses (1-N; 211-212) in electrical communication with a 32-bit host bus (104) in a microcomputer, comprising the following steps: (a) selecting one of said at least two parallel 64-bit system memory buses (1-N; 211-212); (b) retrieving 64 data bits from said one of said at least two parallel 64-bit system memory buses (1-N; 211,212), (c) electrically transmitting a first set of 32 data bits of said 64 data bits onto said 32-bit host bus (104), and (d) electrically transmitting a second set of 32 data bits of said 64 data bits onto said 32-bit host bus (104).
Claim 9
Independent Claim
108 words
A method of transferring data bits from a 64-bit system memory bus (1-N; 211,212) onto a 32-bit host bus (104) in a microcomputer having a system memory (102,202) with at least two parallel 64-bit system memory buses (1-N; 211,212) in electrical communication with a 32-bit host bus (104), comprising the following steps: (a) providing two 32-bit latching transceivers (211A, 211B; 212A, 212B) for each said 64-bit system memory bus (211,212) adapted to access 64 data bits in parallel from said 64-bit system memory bus (211,212), (b) activating alternatively the said latching transceivers (211A, 211B; 212A, 212B) to thereby transfer 32 data bits onto said 32-bit host bus (104).
Claim 10
Independent Claim
218 words
A method of transferring data bits from a 64-bit system memory bus (1-N; 211,212) onto a 32-bit host bus (104) in a microcomputer system memory (102,202) having said 64-bit system memory bus (1-N; 211,212) in parallel electrical communication with said 32-bit host bus (104) via two parallel 32-bit latching transceivers (211A, 211B; 212A, 212B), the method comprising the following steps: (a) reading a first set of 64 data bits from said 64-bit system memory bus (1-N; 211,212) into said two parallel latching transceivers (211A, 211B; 212A, 212B), (b) activating a first latching transceiver (211A, 211B; 212A, 212B) to thereby transfer a first set of 32 data bits onto said 32-bit host bus (104), (c) activating a second latching transceiver (211A, 211B; 212A, 212B) to thereby transfer a second set of 32 data bits onto said 32-bit host bus (104), (d) reading a second set of 64 data bits from said 64-bit system memory bus (1-N; 211,212) into said two parallel latching transceivers (211A, 211B; 212A, 212B), (e) activating said first latching transceiver (211A, 211B; 212A, 212B) to thereby transfer a third set of 32 data bits onto said 32-bit host bus (104), (f) activating said second latching transceiver (211A, 211B; 212A, 212B) to thereby transfer a fourth set of 32 data bits onto said 32-bit host bus (104).
References Cited (Backward Citations)
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