Tuned ring oscillator and clock generation circuit provided therewith

Claim 1

A tuned ring oscillator circuit characterised by comprising: a ring oscillator (22) including a plurality of inverting stages (26, 28) connected in series in an oscillator ring; programmable frequency divider means (40) for providing coarse control of the repetition rate of an output clock pulse, said programmable divider means having an input terminal coupled to said ring oscillator (22) and having an output terminal at which is provided the output clock pulse; means for interrupting said ring oscillator (22) for a pre-determined time including control gate means (24, 70) for inhibiting propagation of an oscillation signal through said ring oscillator, said control gate means connected in series with said plurality of inverting stages (26, 28) and having a control terminal for controlling propagation of said oscillating signals; programmable delay line means (52, 57) for providing fine control of the repetition rate of the output clock pulse, said programmable delay line means including delay time programming means (58 to 61) for setting a delay time, said programmable delay line means having program input terminals for receiving control signals, having an input terminal coupled to the output terminal of the programmable frequency divider means (40), and having an output terminal coupled to the control terminal of the control gate means (24, 70); and comparison means (100) for comparing the output clock pulse frequency with the frequency of a system reference pulse and for generating control signals for the programmable delay line means (52 to 57) to provide fine adjustment of the delay time of an output clock pulse to tune the frequency of the ring oscillator (22) to the frequency of the system reference pulse.