EP0440242A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Noise reduction circuit for video signal recording/reproduction device
Assignee: Sanyo Electric Co Ltd
•
Filing: 1991-01-31
•
Granted: —
•
Expires: 2011-01-31
Abstract
Abstract A reproduction system noise reduction circuit of a VTR is implemented in combination with a recursive type noise reduction circuit and a non-recursive type noise reduction circuit. The recursive type noise reduction circuit has a characteristic with complimentary relation to that of a recording system vertical emphasis circuit to function as a vertical de-emphasis circuit subjecting a reproduced luminance signal to vertical de-emphasis. The non-recursive type noise reduction circuit cancels noise components without line correlation from the reproduced luminance signal subjected to vertical de-emphasis. It is not necessary to increase noise reduction amount in each noise reduction circuit because vertical de-emphasis and noise reduction are carried out individually. Therefore, degradation of vertical resolution and increase in raining-like noise are prevented.
Inventors
- 👤 Hiroshi Iizuka
- 👤 Mituzou Shirai
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 22:12
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/76; H04N5/91; H04N5/92; H04N5/911; H04N5/923
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
100 words
A noise reduction circuit for a video signal recording/reproduction device comprising non-recursive type vertical emphasis means (22, 23, 24, 25, 26) subjecting a video signal to vertical emphasis at the time of recording, said noise reduction circuit comprising: first noise reduction means (28, 29, 30, 31, 32) of a recursive type for subjecting a reproduced video signal to vertical de-emphasis with a characteristic having complimentary relation to that of said vertical emphasis means, and second noise reduction means (32, 33, 34, 35, 36) of a non-recursive type for canceling noise component not having line correlation from the reproduced video signal.
Claim 2
Dependent Claim
110 words
The noise reduction circuit according to claim 1, wherein said non-recursive type vertical emphasis means comprises first delay means (22) for delaying a video signal to be recorded by nH (n : natural number, H : horizontal period of video signal), first subtracting means (23) for subtracting the output of said first delay means from said video signal to be recorded, first limiter means (24) for limiting the amplitude of the output of said first subtracting means, first multiplying means (25) for attenuating said first limiter means output by a first coefficient, and adding means (26) for adding said first multiplying means output to said video signal to be recorded.
Claim 3
Dependent Claim
147 words
The noise reduction circuit according to claim 2, wherein said first noise reduction means of the recursive type comprises first subtracting means (28, 41) for receiving said reproduced video signal as a positive input, second subtracting means (31, 45) for receiving said reproduced video signal as a positive input, second delay means (32, 46) for delaying the output of said second subtracting means by nH period, said first subtracting means receiving said second delay means output as a negative input for subtracting the same from said reproduced video signal, second limiter means (29, 43) for limiting the amplitude of the output of said first subtracting means output, and second multiplying means (30, 44) for attenuating said second limiter means output by a second coefficient, said second subtracting means receiving said second multiplying means output as a negative input for subtracting the same from said reproduced video signal.
Claim 4
Dependent Claim
120 words
The noise reduction circuit according to claim 3, wherein said second noise reduction means of the non-recursive type comprises said second delay means (32) for delaying the output of said second subtracting means by nH period, third subtracting means (33) for subtracting said second delay means output from said second subtracting means output, third limiter means (34) for controlling the amplitude of the output of said third subtracting means, third multiplying means (35) for attenuating the output of said third limiter means by a third coefficient, fourth subtracting means (36) for subtracting said third multiplying means output from said second subtracting means output, and means (37) for providing the output of said fourth subtracting means as a reproduced video signal.
Claim 5
Dependent Claim
48 words
The noise reduction circuit according to claim 4, wherein first and second coefficients K1 and K2 are selected so that the relationship of K1 ≃ K2 / (1 - K2) is established between coefficient K1 of said first multiplying means and coefficient K2 of said second multiplying means.
Claim 6
Dependent Claim
116 words
The noise reduction circuit according to claim 3, wherein said second noise reductions means of the non recursive type comprises said second delay means (46) for delaying the output of said second subtracting means by nH period, first subtracting means (41) for subtracting the output of said second delay means from said reproduced video signal, fourth limiter means (48) for controlling the amplitude of said first subtracting means output, fourth multiplying means (49) for attenuating said fourth limiter means output by a fourth coefficient, fifth subtracting means (51) for subtracting said fourth multiplying means output from said second subtracting means output, and means (52) for providing said fifth subtracting means output as a reproduced video signal.
Claim 7
Dependent Claim
22 words
The noise reduction circuit according to claim 3, wherein the delay periods of said first and second delay means are 1H period.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.