EP0438706A2
Expired / Lapsed
EP
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High speed cmos drive circuit
Assignee: International Business Machines Corp
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Filing: 1990-12-13
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Granted: —
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Expires: 2010-12-13
Abstract
Abstract CMOS ECL drive circuit for providing regulated ECL logic levels. A CMOS logic circuit (11) is connected by parallel N channel and P channel devices (29, 30) to serially connected N and P channel devices (26, 27). The serially connected N and P channel devices (26, 27) are connected across a CMOS power supply (Vdd, Vss) with gate connections connected to the logic circuit (11). The parallel devices (29, 30) provide a regulating feedback current to one of the serially connected P channel and N channel devices (26, 27) during each of first and second ECL logic states. The feedback current effectively controls the bias on the gate connections of the serially connected P and N channel devices (26, 27). The voltage at the junction of the serially connected P and N channel devices (26, 27) is regulated by each of the parallel connected devices (29, 30).
Inventors
- 👤 Barbara A. Chappell
- 👤 Terry I. Chappell
- 👤 Stanley E. Schuster
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 18:49
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/01; H03K3/011; H03K17/00; H03K17/14; H03K17/145; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K3/356113
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
150 words
A CMOS drive circuit for providing level regulated small signal logic levels comprising: first and second serially connected N channel and P channel devices (26, 27) connected to first and second CMOS power supply connections (Vdd, Vss), one of said devices supplying a voltage representing a logic level to a load connected to a junction of said serially connected devices (26, 27); a feedback circuit (29, 30) connected between said junction and gate connections of said first and second N channel and P channel devices (26, 27); and, CMOS logic circuit means (11) receiving CMOS logic signals connected to apply first and second signal levels intermediate said small signal levels and CMOS logic signal levels, to said gate connections, said feedback circuit (29, 30) providing feedback current to said gate connections for modifying said first and second signal levels establishing third and fourth small signal logic levels at said junction.
Claim 2
Dependent Claim
68 words
The CMOS drive circuit of claim 1 wherein said feedback circuit (29, 30) provides first and second parallel paths, one of which contributes substantially more current to said gate connections when a first CMOS logic level is applied to said CMOS logic circuit means, the other of which contributes substantially more feedback current when a second CMOS logic level is applied to said CMOS logic circuit means (11).
Claim 3
Dependent Claim
26 words
The circuit of claim 1 or 2 further comprising a resistive load (37) connected to said junction for providing a substantially constant impedance for said junction.
Claim 4
Dependent Claim
49 words
The drive circuit of claim 3 wherein said resistive load comprises a P channel and N channel device (45, 46) connected in parallel, serially connecting said junction to a common terminal (35), and having gate connections connected to said first and second CMOS circuit power supply connections (Vdd, Vss).
Claim 5
Dependent Claim
70 words
The drive circuit of anyone of the claims 2 to 4 wherein said first and second parallel paths comprise, respectively, a P channel device and N channel device (29, 30) having gate connections connected through delay means (40, 41, 42, 43) to said logic circuit (11) for delaying conduction of said parallel paths following a transition from one of said CMOS logic levels to another of said CMOS logic levels.
Claim 6
Dependent Claim
188 words
A CMOS drive circuit for providing regulated small signal logic levels comprising: (a) a CMOS logic circuit (11) which receives CMOS logic signals, and produces first and second signal levels intermediate said CMOS logic signal levels and said small signal logic levels on an output connection (A); (b) an N channel device (27) serially connected with a P channel device (26) across first and second power supply connections (Vdd, Vss) of said CMOS logic circuit, said devices having gate connections connected to said CMOS logic circuit output connection (A), a junction of said serially connected N channel and P channel devices comprising an output node (34); and, (c) first and second parallel connected P channel and N channel feedback devices (29, 30) connecting said output node (34) to said CMOS logic circuit (11) output connection (A), one of said feedback transistors (29, 30) and one of said serially connected devices (26, 27) establishing a first logic level on said output node (34), the other of said parallel connected devices and the other of said serially connected devices establishing a second small signal logic level on said output node.
Claim 7
Dependent Claim
32 words
The CMOS drive circuit of claim 6 wherein said parallel connected P channel and N channel devices (29, 30) have gate connections connected to each other and to said output node (34).
Claim 8
Dependent Claim
35 words
The CMOS drive circuit of claim 6 wherein said parallel connected P channel and N channel devices (29, 30) have gate connections connected to each other and to said CMOS logic circuit output connection (A).
Claim 9
Dependent Claim
35 words
The CMOS drive circuit of claim 6 wherein said parallel connected P channel and N channel devices (29, 30) have gate connections connected to said first and second CMOS circuit power supply connections (Vdd, Vss).
Claim 10
Dependent Claim
53 words
The CMOS drive circuit of claim 6 wherein said parallel connected P channel and N channel devices (29, 30) have gate connections connected to be switched by said CMOS logic circuit (11) and are alternately switched into a conduction mode as said CMOS logic circuit switches between said first and second logic states.
Claim 11
Dependent Claim
36 words
The CMOS drive circuit of claim 10 further comprising delay means (40, 41, 42, 43) connecting said gate connections of said parallel P channel and N channel devices (29, 30) to said CMOS logic circuit (11).
Claim 12
Dependent Claim
49 words
The CMOS drive circuit of anyone of the claims 6 to 11 further comprising a load element (37) connected between said output node (34) and a reference potential (VREF) for maintaining said ECL levels at a constant level substantially independent of additional loading conditions on said output node (34).
Claim 13
Dependent Claim
82 words
The CMOS drive circuit of claim 12 wherein said load device comprises: a P channel device (45) connected from said output node (34) to a common terminal (35) having a gate connection connected to a terminal (Vss) of a source of voltage potential of one polarity; and, an N channel device (46) connected from said output node (34) to said common terminal (35) having a gate connection connected to a second terminal of said source of voltage potential of an opposite potential.
References Cited (Backward Citations)
No citation records indexed.
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