Display apparatus

Claim 2

A circuit arrangement as claimed in Claim 1 wherein the page location means comprises: - means for receiving in advance page location information for locating a number of different arrays; and - page table memory means for storing the received page location information for subsequent reproduction in response to received level coordinates.

Claim 3

A circuit arrangement as claimed in Claim 1 or Claim 2 wherein the page location information generated by the page location means includes information defining a linear base address and a width value for the corresponding array.

Claim 4

A circuit arrangement as claimed in Claim 3 wherein the texture address converter comprises: - offset generating means for combining the 2-D texture coordinate pair with the width value and the level coordinate to generate a linear (one-dimensional) offset address; and - linear address generating means for combining the base address with the generated offset to generate a linear physical texture memory address for application to a linearly-addressed texture memory.

Claim 5

A circuit arrangement as claimed in Claim 4 wherein the offset generating means includes means for scaling the two virtual texture coordinates in accordance with a scaling factor defined by the level coordinate.

Claim 6

A circuit arrangement as claimed in Claim 5 wherein the scaling factor is a power of 2 and the scaling means comprises means for bit-shifting a binary representation of each of the 2-D texture coordinates a number of places defined by the level coordinate.

Claim 7

A circuit arrangement as claimed in Claim 5 or Claim 6 wherein the offset generating means comprises means for multiplying one of the scaled 2-D texture coordinates by the width value and adding the product to the other scaled 2-D texture coordinate.

Claim 8

A circuit arrangement as claimed in Claim 7 wherein the width value is a power of two and the multiplying means comprises means for bit-shifting a binary representation of the one scaled coordinate a number of places defined by a width index received from the page location means.

Claim 9

A circuit arrangement as claimed in any preceding claim further comprising: - means for generating n (n=2 or more) further physical addresses to form a group of n+1 physical addresses all corresponding to the same level coordinate but with 2-D texture coordinate pairs offset from the received coordinate pair so as to allow parallel addressing of a patch of n+1 texel values in a stored array.

Claim 10

A circuit arrangement as claimed in any preceding Claim further comprising: - means for generating a further physical address (or group of n+1 physical addresses) corresponding to the same 2-D texture coordinate pair (or group of n+1 texture coordinate pairs) but with a level coordinate offset from the received level coordinate; and - selection means responsive to the page location information whereby the physical address(es) and the further physical address(es) may be applied to different ones of two separate, parallel-addressable texture memory banks.

Claim 11

A display apparatus comprising a host processor with associated main memory for the storage of object primitive data and texture definitions and a display processor with associated display memory and texture memory, the host processor comprising: - means for storing in the texture memory at least one pyramidal or part-pyramidal array of texel values comprising a plurality of two-dimensional (2-D) arrays of texel values representing a given 2-D modulation pattern ("texture") at at least two levels of resolution defined by respective values of a level coordinate; and - means for supplying object primitive data to the display processor, including an indication that a pattern of modulation is to be applied to the object primitive in accordance with texel values stored in the pyramidal array in the texture memory; the display processor comprising: - means for generating from the object primitive data a series of pixel addresses for application to the display memory and a corresponding series of 2-D texture coordinate pairs each with an associated level coordinate, to effect a mapping of the stored modulation pattern onto the object primitive at a level or levels of resolution defined by the associated level coordinate; and - means for receiving each 2-D texture coordinate pair and associated level coordinate and for generating therefrom a physical texture memory address for application to the texture memory; characterized in that the texture memory comprises a linearly addressed (one-dimensional) texture memory, in that the means for storing the pyramidal or part-pyramidal array of texel values comprises means for storing each 2-D array in linear form in the texture memory and means for generating page location information for locating each such array in the texture memory, and in that the means for generating the physical texture memory address comprises a circuit arrangement as claimed in any preceding claim arranged to convert the received texture coordinate pair and level coordinate into a linear physical texture memory address.

Claim 12

A display apparatus as claimed in Claim 11, wherein the linear texture memory is divided into n+1 parallel-addressed memories (n=2 or more), the circuit arrangement is as claimed in Claim 9 and the texel value storage means are arranged to distribute the texel values being stored among the n+1 memories in an interleaved manner so that, for each 2-D coordinate pair applied to the circuit arrangement, texel values for a 2-D patch of texels may be read out in parallel, the display apparatus further comprising 2-D interpolation means responsive to fractional parts of the 2-D texture coordinate pair for combining texel values of a 2-D patch into a single interpolated value.

Claim 13

A display apparatus as claimed in Claim 12 further comprising means for generating a 2-D array of texel values for storage in the texture memory as part of a pyramidal array by causing systematic readout and 2-D interpolation of the texel values in a previously stored 2-D array forming a first level of the pyramidal array, and feedback means for storing the resulting interpolated texel values in the memory (in linear form) to form a 2-D array of texel values to form a second, lower-resolution level of the said pyramidal array.

Claim 14

A display apparatus as claimed in any of Claims 11 to 13, wherein the texture memory comprises separate first and second linearly addressable texture memory banks, the texel value storage means being arranged to store the 2-D arrays forming successive levels of a given pyramidal or part-pyramidal array alternately in the first and second texture memory banks, the circuit arrangement being as claimed in Claim 10 and being arranged to apply the physical address(es) and further physical address(es) to the first and second texture memory banks in such a manner that texel values for two adjacent levels of a given pyramidal array may be read out in parallel, the display apparatus further comprising an interpolator responsive to a fractional part of the level coordinate for combining texel values from both levels into a single interpolated texel value.