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EP0437044A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Data processing system with instruction tag apparatus

Assignee: International Business Machines Corp
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Filing: 1990-12-07
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Granted: —
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Expires: 2010-12-07
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Abstract

Abstract A data processing system having an instruction execution circuit 16 that executes a first type of instruction. Also included is a fetch circuit that fetches instructions from a memory 10 and fetches data from the memory in response to a second type of instruction. An instruction decoder is included that decodes fetched instructions and dispatches instructions of the first type to an instruction queueing circuit. The instruction decoder further dispatches instructions of the second type to the fetching circuit. The instruction queueing circuit includes the capability to store decoded instructions of the first type in a queue 30 while tagging these instructions when data required for the execution of these instructions has not been fetched. The instruction queueing circuit further clears these tags of these instructions of the first type when data that is required for the execution has been fetched. The instruction queueing circuit serially provides the untagged instructions of the first type to the instruction execution circuit.

Inventors

  • 👤 Troy Neal Hicks
  • 👤 Myhong Nguyenphu

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-02 13:26
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F9/3889; G06F9/3836

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 179 words
A data processing system having a main memory 10, an instruction means 12 to supply arithmetic instructions and load instructions, the load instructions being used to fetch data from the main memory 10 required for the execution of the arithmetic instructions, and buffering means 30, 34 in which the instructions are queued before execution, characterised in that the system includes decoding means 26, 28 to decode the instructions and to separate arithmetic instructions into a first queue in the buffering means and load instructions into a second queue in the buffering means, a first processor 16 to process the arithmetic instructions and a second processor 14 to process the load instructions asynchronously with the arithmetic instructions, tag control means 68 to store a tag for each arithmetic instruction in the first queue which requires data to be fetched by a load instruction in the second queue, and to cancel the tag for each arithmetic instruction when the data for that instruction has been fetched, the first processor 16 being arranged to execute arithmetic instructions which have no stored tag.
Claim 2
Dependent Claim 23 words
A system according to claim 1 in which the decoding means 26, 28 includes first and second decoders for decoding two instructions simultaneously.
Claim 3
Dependent Claim 68 words
A system according to claim 1 or 2 wherein the buffering means 30, 34 includes a plurality of ordered arithmetic instruction buffers 50, 54, 58, 62 and tag storage 52, 56, 60 and 64 to store the arithmetic instructions in an ordered sequence with their respective tags, and means to change the order of the arithmetic instructions and corresponding tags in response to execution of the load instructions.
Claim 4
Dependent Claim 44 words
A system according to claim 1, 2 or 3 wherein the first processor 16 is a floating print processor and the second processor 14 is a fixed point processor which processes the load instructions to provide floating point data to the floating point processor.

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