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EP0436958A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Cell signal processing circuit and optical switch apparatus using the same

Assignee: Hitachi Ltd
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Filing: 1990-12-28
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Granted: —
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Expires: 2010-12-28
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Abstract

Abstract A cell signal processing circuit is provided which is capable of precisely extracting a timing signal and a cell synchronizing signal. The cell signal processing circuit is principally composed of an signal adder circuit (2) for adding a dummy signal comprising bit signals in a direct current balanced state to an end portion of respective inputted time series cell signals, and a separator circuit (12) for separating and out-putting the time series cell signals. The dummy signal composed of the same number of bits "0" and "1" is added to input signals in the form of time series cells such that signal cells are exchanged at a time of a bit "0" in the dummy signal. An optical switch apparatus using the above-mentioned cell signal processing circuit as an optical switch array (8) is also provided which includes a photoelectric converter (9) for converting the time series optical cell signal to an electric signal, a clock recovery circuit (13) for extracting a clock signal from an output from the photoelectric converter, a cell synchronization circuit (14) for extracting a cell synchronizing signal from the output from the photoelectric converter, and a decision circuit (11) for decision the output from the photoelectric converter by the use of the clock signal. The optical switch apparatus of the invention has a simple circuit arrangement which is not influenced by data loss and jitter.

Inventors

  • 👤 Yasushi Takahashi
  • 👤 Eiichi Amada
  • 👤 Kimiaki Ando
  • 👤 Masanori Miyata

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-03 06:38
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0605; H04Q11/0001; H04Q11/0062; H04Q11/0066

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 75 words
A cell signal processing circuit comprising: first means (2) for adding a dummy signal comprising bit signals in a direct current balanced state to an end portion of respective inputted time series cell signals; and second means (12) for separating said time series cell signals with said dummy signals added thereto at a position of said respective dummy signals, processing the respective separated cell signals in cell units, and outputting the time series cell signals.
Claim 2
Dependent Claim 24 words
A cell signal processing circuit according to claim 1, wherein said separation is carried out at a "0" bit position of said dummy signal.
Claim 3
Dependent Claim 41 words
A cell signal processing circuit according to claim 1 or 2, wherein an electric-photo converter (6) and a photoelectric converter (9) are provided between said first means and said second means and at an output section of said second means, respectively.
Claim 4
Dependent Claim 116 words
An optical switch apparatus which is adapted to convert an inputted electric signal the form of time series cells to an optical signal by an electric-photo converter (6), performing a change-over operation by optical switch means (8) and exchanging the inputted signal, comprising: first means (2) coupled to an input section of said electric-photo converter for adding a dummy signal comprising bit signals in a direct current balanced state to an end portion of said respective input signal cells, wherein said optical switch means separates said input signal cells with said dummy signals added thereto at positions of said dummy signals, exchanges said separated cell signals in cell units, and outputs a time series optical signal.
Claim 5
Dependent Claim 23 words
An optical switch apparatus according to claim 4, wherein said separation is carried out at a "0" bit position of said dummy signal.
Claim 6
Dependent Claim 99 words
An optical switch apparatus according to claim 4 or 5 further comprising, a photoelectric converter (9) coupled to an output section of said optical switch means for converting said time series optical cell signal to an electric signal, a clock recovery circuit (13) for extracting a clock signal from an output from said photoelectric converter, a cell synchronization circuit (14) for extracting a cell synchronizing signal from an output from said photoelectric converter, and a decision circuit (11) for decision the output from said photoelectric converter by the use of the clock signal extracted by said clock recovery circuit.
Claim 7
Dependent Claim 39 words
An optical switch apparatus according to claim 6, wherein said cell synchronization circuit has a filter (15) being tuned with a switching cycle frequency which comprises a circuit for extracting a cell cycle frequency component from said dummy signal.
Claim 8
Dependent Claim 39 words
An optical switch apparatus according to claim 7, wherein said dummy signal is scrambled, and said dummy signal is composed of the same number of identical sequential codes, said number being not less than the number of scramble stages.
Claim 9
Dependent Claim 43 words
An optical switch apparatus according to claim 6, wherein said cell synchronization circuit is supplied with a clock signal from said clock recovery circuit and an output from said decision circuit, and formed of a logical processing circuit for detecting said dummy signal.
Claim 10
Dependent Claim 43 words
An optical switch apparatus according to claim 7, 8 or 9, wherein said dummy signal is composed of a sequence of bit signals "0" and a sequence of bit signals "1" including the same bit number as said sequence of bit signals "0".
Claim 11
Dependent Claim 72 words
An optical switch apparatus according to claim 4, wherein said dummy signal is composed of a sequential bit signal "0" having a length longer than a time period required to change over said optical switch stages and a phase deviation period among a plurality of optical cell signals inputted to said optical switching stages and a sequential bit signal "1" having the same length as that of said sequential bit signal "0".

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