EP0436387B1
Expired / Lapsed
EP
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Single chamber via etch through a dual-layer dielectric
Assignee: HP Inc
•
Filing: 1990-12-27
•
Granted: 2000-08-23
•
Expires: 2010-12-27
Abstract
No abstract record available.
Inventors
- 👤 Valerie A. Bach
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 22:32
CPC Classifications
C; C04; C04B; C04B41/00; C04B41/009; C04B41/53; C04B41/5338; C04B41/5346; C04B41/80; C04B41/91; H; H10; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/082; C04B2111/00; C04B2111/00474; C04B2111/00844
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
204 words
A method of forming vias (10) in a dual-layer
dielectric including a silicon oxide layer (18) formed on an
integrated circuit substrate (12, 14) and a silicon nitride
layer (20) formed on the oxide layer, the method comprising: forming a photoresist layer (22) atop the nitride
layer; patterning the photoresist layer to define a via hole
(24) therein; in a single processing chamber, successively etching
each of the nitride and oxide layers (20, 18) through the
via hole (24) defined in the photoresist layer (24) to
form a tapered via hole (10) through the dual-layer
dielectric, a sidewall (32) of said tapered via hole (10)
having a profile defining an inward and downward tapered
continuous surface, characterised in that said etching
comprises a first substep of predominantly anisotropic plasma etching the
nitride layer simultaneously with the photoresist layer (22)
and preferentially over the oxide layer (18) with a fluorine
compound and oxygen diluted with an inert gas to create a
tapered via hole to the oxide layer (18), followed by a second
substep of predominantly anisotropic plasma etching the oxide layer
(18) preferentially over the nitride layer and over the photoresist layer
with a fluorine compound diluted with an inert gas but without oxygen.
Claim 2
Dependent Claim
45 words
A method according to Claim 1 wherein the integrated
circuit substrate includes a first conductive layer (16, 17)
underlying the dual-layer dielectric, the etching of the
oxide layer (18) being controlled so as to etch the oxide
layer (18) preferentially over the conductive layer (17).
Claim 3
Dependent Claim
23 words
A method according to Claim 1 or Claim 2, wherein the
plasma etching steps are carried out at a frequency of 400
kHz.
Claim 4
Independent Claim
38 words
A method according to any proceeding Claim which
includes controlling power of a plasma in which the etching
processes are performed so as to vary the selectivity of
each etching process to oxide and to nitride, in turn.
Claim 5
Dependent Claim
73 words
A method according to Claim 4 in which the power is set
in the nitride etching process at a first power level such
that the photoresist and nitride layers (22,20) are etched
at approximately equal etch rates greater than an etch rate
for the oxide layer (18), and is set in the oxide etching
process at a second, increased power level such that the
etch rate for the oxide layer (18) is increased.
Claim 6
Independent Claim
43 words
A method according to any preceding claim wherein the
integrated circuit substrate includes a first conductive
layer (16, 17) underlying the dual-layer dielectric, and
including the step of depositing a conductive layer atop the
dual-layer dielectric including into said tapered via hole
(10).
References Cited (Backward Citations)
No citation records indexed.
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