EP0436387A2
Expired / Lapsed
EP
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Single chamber via etch through a dual-layer dielectric
Assignee: HP Inc
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Filing: 1990-12-27
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Granted: —
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Expires: 2010-12-27
Abstract
Abstract Tapered via holes (10) of uniform diameter are formed in a dual-layer (SiO₂/SiNi) dielectric (18, 20) used for isolation of metallization layers in an integrated circuit. The method includes forming a photoresist layer (22) atop the nitride layer (20) and patterning the photoresist to define a via hole (24). The nitride and oxide layers are successively plasma etched through the photoresist-defined via holes (24) to form via holes (26, 28) through the dual-layer dielectric to an underlying metal line (16, 17). Etching of the nitride layer is selective to the oxide layer. Etching of the oxide layer is selective to the metal line. The photoresist and nitride layers are etched simultaneously in the presence of oxygen so as to taper the via hole in the nitride. The oxide is etched in the absence of oxygen, producing a tapered sidewall profile (32) extending continuously to the metal.
Inventors
- 👤 Valerie A. Bach
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 06:09
CPC Classifications
C; C04; C04B; C04B41/00; C04B41/009; C04B41/53; C04B41/5338; C04B41/5346; C04B41/80; C04B41/91; H; H10; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/082; C04B2111/00; C04B2111/00474; C04B2111/00844
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
107 words
A method of forming vias (10) in a dual-layer dielectric including a silicon oxide layer (18) formed on an integrated circuit substrate (12, 14) and a silicon nitride layer (20) formed on the oxide layer, the method comprising: forming a photoresist layer (22) atop the nitride layer; patterning the photoresist layer to define a via hole (24) therein; and successively etching each of the nitride and oxide layers (20, 18) through the via hole defined in the photoresist layer (24) to form a via hole (10) through the dual-layer dielectric; etching the nitride layer (20) including plasma etching the nitride layer selectively to the oxide layer (18).
Claim 2
Dependent Claim
33 words
A method according to claim 1 in which the step of etching the nitride and oxide layers (20, 18) successively includes plasma etching the oxide layer (18) selectively to the nitride layer (20).
Claim 3
Dependent Claim
41 words
A method according to claim 2 wherein the integrated circuit substrate includes a first conductive layer (16, 17) underlying the dual-layer dielectric, the etching of the oxide layer (18) being controlled so as to be selective to the conductive layer (17).
Claim 4
Dependent Claim
34 words
A method according to claim 1 including controlling the etching step so as to form the via hole (10) with a sidewall (32) having a profile defining an inward and downward tapered continuous surface.
Claim 5
Dependent Claim
36 words
A method according to claim 1 wherein the integrated circuit substrate includes a first conductive layer (16, 17) underlying the dual-layer dielectric, including depositing a conductive layer atop the dual-layer dielectric including into said via hole.
Claim 6
Independent Claim
126 words
A method of forming vias (10) in a dual-layer dielectric including a silicon oxide layer (18) formed on an integrated circuit substrate (12, 14) and a silicon nitride layer (20) formed on the oxide layer, the method comprising: forming a photoresist layer (22) atop the nitride layer (20); patterning the photoresist layer to define a via hole (24) therein; plasma etching each of the nitride and oxide layers (20, 18) in first and second processes through the photoresist-defined via hole (24) to form a via hole (10) through the dual-layer dielectric; and controlling each of the plasma etching processes so as to form the via hole (10) in the dual-layer dielectric with a sidewall (32) having a profile defining an inward and downward tapered continuous surface.
Claim 7
Dependent Claim
39 words
A method according to claim 6 in which the controlling step includes controlling chemical composition of a plasma atmosphere in which the etching processes are performed so as to etch the photoresist layer simultaneously with etching the nitride layer.
Claim 8
Dependent Claim
38 words
A method according to claim 7 in which the controlling step includes providing a flow of oxygen during the nitride etching process to aid in contouring the photoresist-defined via hole (24) to an inward and downward tapered shape
Claim 9
Dependent Claim
41 words
A method according to claim 6 in which the controlling step includes controlling power of a plasma in which the etching processes are performed so as to vary the selectivity of each etching process to oxide and to nitride, in turn.
Claim 10
Dependent Claim
74 words
A method according to claim 9 in which the power is set in the nitride etching process at a first power level such that the photoresist and nitride layers (22, 20) are etched at approximately equal etch rates greater than an etch rate for the oxide layer (18), and is set in the oxide etching process at a second, increased power level such that the etch rate for the oxide layer (18) is increased.
References Cited (Backward Citations)
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