EP0436211A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method and apparatus for observing internal memory-mapped registers
Assignee: National Semiconductor Corp
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Filing: 1990-12-22
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Granted: —
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Expires: 2010-12-22
Abstract
Abstract A method and apparatus for observing the contents on internal memory-mapped registers of controllers and co-processors which have been integrated on-chip with a central processing unit ("CPU"). The CPU asserts a first signal when access to internal memory is requested and deactivates a second signal which would normally allow simultaneous access to both internal and external memory locations. In this way, the contents of internal memory may be observed in real time.
Inventors
- 👤 Zeev Bikowsky
- 👤 Dan Biran
- 👤 Gideon Intrater
- 👤 Yair Hadas
- 👤 Zohar Peleg
- 👤 Aharon Ostrer
- 👤 Yigal Ben-Zeev
- 👤 David Lidor
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 18:25
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G06F11/3656; G06F13/00; G06F13/10; G06F13/12
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
192 words
An integrated data processing system that includes a central processing unit (CPU) which is connected by a system bus, including an address bus and a data bus, to at least one external device, said external device having external registers located therein, wherein the CPU initiates external bus cycles to communicate with said external registers via said system bus by activating a first signal to allow said system bus to communicate with said external registers, and wherein the CPU generates a second signal, the value of which determines the direction of communication with said external registers on said system bus, and wherein data to be transferred is presented on said data bus, said data processing system comprising: at least one integrated peripheral system component, said component including status and control registers which are referenced as memory-mapped registers ("internal memory-mapped registers"); means for deactivating said first signal such that system bus communication with said external registers is disabled; means for activating a third signal which allows said system bus to communicate with said internal memory-mapped registers; and means for accessing said internal memory-mapped registers and placing the information contained therein on the data bus.
Claim 2
Dependent Claim
17 words
A data processing system according to claim 1, wherein said integrated peripheral system component is a co-processor.
Claim 3
Dependent Claim
17 words
A data processing system according to claim 1, wherein said integrated peripheral system component is a controller.
Claim 4
Independent Claim
199 words
A method of observing the contents of internal memory-mapped registers of an integrated data processing system which includes a central processing unit (CPU) which is connected by a system bus, including an address bus and a data bus, to at least one external device, said external device having external registers located therein wherein the CPU initiates external bus cycles to communicate with said external registers via said system bus by activating a first signal to allow said system bus to communicate with said external registers, and wherein the CPU generates a second signal, the value of which determines the direction of communication with said external registers on said system bus, and wherein data to be transferred is presented on the data bus, said method comprising: integrating at least one peripheral system component with said CPU on-chip, said peripheral system component including status and control registers, said registers being referenced as memory-mapped registers ("internal memory-mapped registers"); deactivating said first signal such that system bus communication with said external registers is disabled; activating a third signal which allows system bus communication with said internal memory-mapped registers; accessing said internal memory-mapped registers and placing the information contained therein on the data bus.
References Cited (Backward Citations)
No citation records indexed.
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