System for partitioning and testing submodule circuits of an integrated circuit

Claim 2

The circuit of claim 1 characterized in that each switch further comprises first and second transmission gates connected together at one end.

Claim 3

The circuit of claim 2 characterized in that the means for configuring the at least one switch comprise a plurality of flip-flops, each associated with at least one of said transmission gates, said flip-flops being arranged in series to receive on a data-in conductor a bit data pattern, the first and second transmission gates within a single switch being associated with separate ones of the flip-flops.

Claim 4

The circuit of claim 3 wherein said flip-flops are D-type flip-flops, further including a clock input connected together.

Claim 5

A circuit for testing electronic submodules on a common substrate, at least one of said submodules having an input for receiving an output signal of a preceding submodule comprising: a test bus comprising a plurality of conductors connected at one end to a plurality of test pads on said substrate; an intermediate analog switch located adjacent each input of a submodule having an output terminal connected to said submodule input, and an input terminal connected to an output of a preceding submodule, and an input/output terminal connected to one of said plurality of conductors; an input analog multiplexer having an input connected to a signal input pad of said common substrate, a first output to one of said test bus conductors, and a second output connected to an input of said preceding submodule, selectively permitting a signal to be supplied from said signal input to said preceding submodule and said one test bus conductor; an output analog multiplexer having a first input connected to an output of said succeeding submodule, a second input terminal connected to said one test bus conductor, and an output terminal connected to a signal output pad; and, a plurality of flip-flops, each flip-flop being located adjacent each of said analog switches and multiplexers and connected to operate each analog switch and multiplexer to effectively isolate each submodule, and provide a signal to individual isolated submodules, and provide an output signal from said isolated submodules to said test pad.

Claim 6

A circuit for testing electronic submodules according to claim 5 further comprising: a second intermediate analog switch located at a second input of said preceding module, having an input connected to a second output connection of said succeeding module, an input/output connection connected to a second conductor of said test bus, and an output connection connected to said preceding module second input, said analog switch being connected to one of said flip-flops for isolating said preceding module second input from said succeeding module; and, an input/output test pad connected to said second conductor for receiving or supplying a signal to said input/output connection of said second intermediate analog switch.

Claim 7

The circuit of claim 5 further comprising a data input pad on said substrate, connected to supply data to each of said flip-flops.

Claim 8

The circuit of claim 6 further comprising a reset pad on said substrate connected to reset said flip-flops, said reset flip-flops establishing input/output connections of said modules to a normal configuration.

Claim 9

The circuit of claim 7 wherein said flip-flops are serially connected, and a test data configuration is shifted into said flip-flops through said data input pad.

Claim 10

In an integrated circuit having a plurality of circuit elements comprising a plurality of submodules, one of said submodules including an output connected to an input of an adjacent module, and an input connected to an output of said adjacent module, a circuit for testing said submodules individually comprising: first and second analog switches located adjacent respective of said inputs having a first connection connected to said inputs, a second connection connected to outputs of an adjacent submodule, and third connections; a test bus on said integrated substrate having a first conductor connected to said first analog switch third connection, and a second conductor connected to said second analog switch third connection; and, first and second digital flip-flop circuits located adjacent respective of said first and second analog switches, said digital flip-flops having a data input for receiving test data which identifies a test state for said analog switches, whereby input and output connections of one of said modules are connected to said first and second conductors.

Claim 11

The circuit for testing of claim 10 further comprising: an analog multiplexer connecting an input pad of said integrated circuit to said first test bus conductor, and a second input of said one submodule; and, a third flip-flop connected to said analog multiplexer for permitting a signal to be selectively routed through said input pad to said one submodule second input, or said test bus first conductor.

Claim 12

The circuit of claim 11 further comprising: a second analog multiplexer connected to said test bus first conductor, and to a second output of said adjacent module, and having an output terminal connected to an output pad on said substrate; and, a fourth flip-flop connected to switch said second analog multiplexer in response to test data supplied to said fourth flip-flop, whereby an output signal from said one submodule may be applied through said first analog switch and second analog multiplexer to said output pad.

Claim 13

The circuit of claim 12 further comprising: a third analog multiplexer connected to said test bus second conductor, and to an input/output pad; and, a fifth flip-flop connected to enable said third analog multiplexer in response to said test data.

Claim 14

The circuit of claim 10 wherein said digital flip-flops are D-type flip-flops having data inputs serially connected together with a data input pad on said integrated circuit, said flip-flops having a clock connection connected to a test clock pad on said substrate, permitting test data to be serially supplied to said flip-flops to identify a submodule to be tested.

Claim 15

The circuit of claim 14 further comprising a mode control pad on said substrate connected to a reset input of said flip-flops which permit said test data to be cleared from said flip-flops.

Claim 17

A system for providing a testing capability according to claim 16 wherein said analog switch means interrupt normal submodule interconnections when enabled by said digital logic control means, and restore normal submodule interconnections when disabled by said digital logic means.

Claim 18

The system of claim 17 wherein said first multiplexer has input connections which supply signals to be asserted on said number of ports to be controlled when enabled, and which receive normal module input signals when disabled by said digital logic means, supplying said normal module input signals to input ports of said submodules for normal circuit operation.

Claim 19

The system of claim 17 wherein said second multiplexer is connected to output ports of said submodules for providing normal module operating signals from said ports when disabled by said digital logic means.

Claim 20

The system of claim 16 wherein said digital logic means comprise a plurality of D flip-flops serially connected to each other, each D flip-flop being located adjacent a respective analog multiplexer or analog switch means, and connected to control said adjacent multiplexer or analog switch means.

Claim 21

The system of claim 20 wherein said serially connected D flip-flops are connected to receive serial data defining a test pattern in response to a clock signal.

Claim 22

The system of claim 21 wherein said D flip-flops have a reset input which restores said analog multiplexer and analog switch means to a disabled condition, permitting normal circuit operation.

Claim 23

The circuit of claim 3, further comprising a plurality of three-way analog switches, the input connection of the first transmission gate in each switch being coupled with a first one of the flip-flops, the input connection of the second transmission gate in each switch being coupled with a second one of the flip-flops.

Claim 24

The circuit of claim 3 wherein a) the first transmission gate has: i) an input coupled with a first one of the flip-flops; ii) an input/output connection coupled with the test bus; and iii) an output coupled with the succeeding submodule; and b) the second transmission gate has: i) a first input coupled with the preceding submodule; ii) a second input coupled with a second one of the flip-flops; and iii) an output coupled with the output of the first transmission gate.

Claim 25

The circuit of claim 3 wherein the three-way analog switch further comprises a third transmission gate coupled between the input connection of the three-way analog switch and the input/output connection of the three-way analog switch.

Claim 26

The circuit of claim 3 further comprising a data input connection connected to supply data to said flip-flops, and wherein the first and second flip-flops are serially connected, and a test data configuration is shifted into said flip-flops through said data input connection.

Claim 27

The circuit of claim 3 further comprising a reset connection connected to reset said flip-flops, said reset establishing input/output connections of said modules to a normal configuration.