Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
207 words
A data processing system having a processor 18, an internal memory 20, an internal bus 22, a peripheral bus 36, and a channel controller 14 for controlling the transfer of data between the memory 20 and a plurality of peripheral devices 24, 26 and 28 through the internal bus 22 and through the peripheral bus 36, the channel controller including data buffers 38, 40, 42 to buffer the transfer of data to or from a respective peripheral device, and the controller 14 including priority arbitration means 68 for granting data transfer requests to contending peripheral devices according to a predetermined priority ranking, characterised in that a data transfer over the peripheral bus requires plural cycles of operation to fill or to empty any one of the data buffers, and priority conditioning means 70, 72, 74 are provided to generate a conditioning signal when a data buffer 38, 40, 42 is not ready to transfer data to or from the internal bus 22, the priority arbitration means 68 being arranged to adapt the said priority ranking by lowering the priority of a data transfer request to or from a peripheral device when the priority conditioning means signals that the respective data buffer is not ready to transfer data.
Claim 2
Dependent Claim
39 words
A system according to claim 1 wherein the conditioning means 70, 72, 74 generates a conditioning signal for a data transfer request to transfer data from a peripheral to the respective data buffer when that data buffer is full.
Claim 3
Dependent Claim
41 words
A system according to claim 1 or 2 wherein the conditioning means 70, 72, 74 generates a conditioning signal for a data transfer request to transfer data from a data buffer to the memory 20 when that data buffer is empty.
Claim 4
Dependent Claim
38 words
A system according to claim 1, 2, or 3 wherein internal bus requires one cycle of operation to transfer 32 bits of data and the peripheral bus requires two or more cycles to transfer 32 bits of data.
Claim 5
Dependent Claim
115 words
A data processing system incorporating buffered direct memory addressing from a plurality of peripherals 24, 26, 28 through a peripheral bus 36, a channel controller 14 and an internal bus 22, the internal bus 22 operating at higher speed than the peripheral bus 36 and the controller 14 incorporating means 68 to grant data transfer requests in accordance with a predetermined priority ranking characterised in that conditioning means 70, 72, 74 are provided to adapt the priority ranking whenever the internal bus 22 can make a data transfer for a peripheral of lower priority ranking but must wait for the peripheral bus 36 to make a data transfer for a peripheral of higher priority ranking.