Driver circuit

Claim 2

The circuit of claim 1, wherein said counter circuit decimates said clock pulses by a factor equal to or greater than said first number minus said second number.

Claim 3

A cascaded driver circuit having two or more stages connected in common to a serial data signal line, a clock pulse signal line, and a latch pulse signal line, each stage comprising: a first terminal connected to said serial data signal line, for input of serial data; a second terminal connected to said clock pulse signal line, for input of a clock pulse signal; a third terminal connected to said latch pulse signal line, for input of a latch pulse signal; a fourth terminal for input of an enable input signal from a preceding stage; a fifth terminal for output of an enable output signal to a next stage; a counter circuit connected to said second terminal, for decimating said clock pulse signal by a factor of D, where D is an integer greater than or equal to two, thus generating decimated clock pulses; an enable latch circuit, connected to said fourth terminal and said counter circuit, for latching said enable input signal on said decimated clock pulses; a shift register comprising N + 1 flip-flops connected in series, from a first flip-flop to an (N + 1)-th flip-flop, N being a positive integer, for shifting a data latching signal sequentially from said first flip-flop to said (N + 1)-th flip-flop according to said clock pulse signal, thereby generating a sequence of N data latching signals as outputs of flip-flops from said first flip-flop through an N-th flip-flop of said shift register; a data latching circuit comprising N flip-flops connected to said first terminal and said shift register, for latching N bits of said serial data on said N data latching signals; a clock control circuit connected to said second terminal, said shift register, and said enable latch circuit, for passing said clock pulse signal to said shift register from a time when said enable latch circuit latches said enable signal until said data latching signal is shifted from said N-th flip-flop into said (N + 1)-th flip-flop in said shift register; an enable output circuit, connected to said third terminal, said fifth terminal, and said shift register, for deasserting said enable output signal responsive to said latch pulse signal, and asserting said enable output signal when said data latching signal is shifted into an (N - E)-th flip-flop in said shift register, where O < E < D.

Claim 4

The circuit of claim 3, wherein D = 2, E = 1, and N is an even integer.

Claim 5

The circuit of claim 4, wherein said counter circuit comprises: a T-type flip-flop clocked by said clock pulse signal; and an AND gate for ANDing said clock pulse signal with an output of said T-type flip-flop, thus generating said decimated clock pulses.

Claim 6

The circuit of claim 5, wherein said T-type flip-flop is reset by said latch pulse signal.

Claim 7

The circuit of claim 3, wherein D > 2, and flip-flops from an (N - D + 1)-th flip-flop to an (N - 1)-th flip-flop in said shift register have switches for selecting one flip-flop thereamong as said (N - E)-th flip-flop.

Claim 8

The circuit of claim 3, wherein D = 4 and said counter circuit comprises: a first T-type flip-flop clocked by said clock pulse signal; a second T-type flip-flop clocked by an output of said first T-type flip-flop; and an AND gate for ANDing said clock pulse signal with outputs of said first T-type flip-flop and said second T-type flip-flop, thus generating said decimated clock pulses.

Claim 9

The circuit of claim 8, wherein said first T-type flip-flop and said second T-type flip-flop are reset by said latch pulse signal.